
TEST CIRCUIT
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
CL*
* Includes all probe and jig capacitance
Figure 5.
CLOCK
RESET
SERIAL DATA J
INPUTS K
SERIAL SHIFT/
PARALLEL LOAD
A
PARALLEL
DATA
B
INPUTS C
D
QA
PARALLEL DATA QB
OUTPUTS
QC
QD
RESET
TIMING DIAGRAM
H
L
H
L
SERIAL SHIFT
LOAD
MC74HC195
SERIAL SHIFT
High–Speed CMOS Logic Data
3–5
DL129 — Rev 6
MOTOROLA