QL3060(RevB) 데이터 시트보기 (PDF) - QuickLogic Corporation

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QL3060
(Rev.:RevB)

60,000 Usable PLD Gate pASIC3 FPGA Combining High Performance and High Density

QuickLogic Corporation 

Military Plastic pASIC 3 Family

PRODUCT SUMMARY

Product Summary

The pASIC 3 FPGA family features up to 60,000

usable PLD gates. pASIC 3 FPGAs are fabricated

on a 0.35mm four-layer metal process using Quick-

Logic’s patented ViaLink technology to provide a

unique combination of high performance, high den-

sity, low cost, and extreme ease-of-use.

The pASIC 3 product family contains 1,584 logic

cells. With a maximum of 316 I/Os, and is available

in 208-PQFP and 84-PLCC packages.

Software support for the complete pASIC 3 family is

available through three basic packages. The turnkey

QuickWorks® package provides the most complete

FPGA software solution from design entry to logic

synthesis, to place and route, to simulation. The

QuickWorksTM-Lite and QuickToolsTM packages pro-

vide a solution for designers who use Cadence,

Exemplar, Mentor, Synopsys, Synplicity, Viewlogic,

Veribest, or other third-party tools for design entry,

synthesis, or simulation.

Pinout Diagram 68-Pin CPGA

PINOUT DIAGRAM 84-PIN PLCC

TABLE 2: 84-pin PLCC

8-24

24

Preliminary

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