FDG6303N(2001) 데이터 시트보기 (PDF) - Fairchild Semiconductor
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FDG6303N Datasheet PDF : 5 Pages
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September 2001
FDG6303N
Dual N-Channel, Digital FET
General Description
These dual N-Channel logic level enhancement mode
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This
very high density process is especially tailored to
minimize on-state resistance. This device has been
designed especially for low voltage applications as a
replacement for bipolar digital transistors and small
signal MOSFETs.
Features
25 V, 0.50 A continuous, 1.5 A peak.
RDS(ON) = 0.45 Ω @ VGS= 4.5 V,
RDS(ON) =0.60 Ω @ VGS= 2.7 V.
Very low level gate drive requirements allowing direct
operation in 3 V circuits (VGS(th) < 1.5 V).
Gate-Source Zener for ESD ruggedness
(>6kV Human Body Model).
Compact industry standard SC70-6 surface
mount package.
SC70-6
SOT-23
SuperSOTTM-6
SuperSOTTM-8
SO-8
SOT-223
S2
G2
D1 .03
SC70-6
D2
S1 G1
1 or 4 *
2 or 5
3 or 6
* The pinouts are symmetrical; pin 1 and 4 are interchangeable.
Units inside the carrier can be of either orientation and will not affect the functionality of the device.
Absolute Maximum Ratings TA = 25°C unless otherwise noted
Symbol Parameter
VDSS
Drain-Source Voltage
VGSS
Gate-Source Voltage
ID
Drain/Output Current - Continuous
- Pulsed
PD
Maximum Power Dissipation
(Note 1)
TJ,TSTG Operating and Storage Temperature Range
ESD
Electrostatic Discharge Rating MIL-STD-883D
Human Body Model (100 pF / 1500 Ω)
THERMAL CHARACTERISTICS
RθJA
Thermal Resistance, Junction-to-Ambient
FDG6303N
25
- 0.5 to +8
0.5
1.5
0.3
-55 to 150
6.0
415
6 or 3
5 or 2
4 or 1 *
Units
V
V
A
W
°C
kV
°C/W
FDG6303N Rev.F
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