EX64-CS100A 데이터 시트보기 (PDF) - Actel Corporation

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EX64-CS100A

eX Family FPGAs

Actel Corporation 

eX Family FPGAs

Clock Resources

eX’s high-drive routing structure provides three clock

networks. The first clock, called HCLK, is hardwired from

the HCLK buffer to the clock select MUX in each R-Cell.

HCLK cannot be connected to combinational logic. This

provides a fast propagation path for the clock signal,

enabling the 3.9 ns clock-to-out (pad-to-pad)

performance of the eX devices. The hard-wired clock is

tuned to provide a clock skew of less than 0.1 ns worst

case. If not used, the HCLK pin must be tied LOW or HIGH

and must not be left floating. Figure 1-5 describes the

clock circuit used for the constant load HCLK.

HCLK does not function until the fourth clock cycle each

time the device is powered up to prevent false output

levels due to any possible slow power-on-reset signal and

fast start-up clock circuit. To activate HCLK from the first

cycle, the TRST pin must be reserved in the Design

software and the pin must be tied to GND on the board.

(See the "TRST, I/O Boundary Scan Reset Pin" on page 1-

26).

The remaining two clocks (CLKA, CLKB) are global routed

clock networks that can be sourced from external pins or

from internal logic signals (via the CLKINT routed clock

buffer) within the eX device. CLKA and CLKB may be

connected to sequential cells or to combinational logic. If

CLKA or CLKB is sourced from internal logic signals, the

external clock pin cannot be used for any other input

and must be tied LOW or HIGH and must not float.

Figure 1-6 describes the CLKA and CLKB circuit used in eX

devices.

Table 1-1 describes the possible connections of the

routed clock networks, CLKA and CLKB.

Unused clock pins must not be left floating and must be

tied to HIGH or LOW.

HCLKBUF

Figure 1-5 • eX HCLK Clock Pad

Constant Load

Clock Network

CLKBUF

CLKBUFI

CLKINT

CLKINTI

Figure 1-6 • eX Routed Clock Buffer

Table 1-1 • Connections of Routed Clock Networks, CLKA

and CLKB

Module

Pins

C-Cell

A0, A1, B0 and B1

R-Cell

CLKA, CLKB, S0, S1, PSET, and CLR

I/O-Cell

EN

Clock Network

From Internal Logic

1-4

v4.3

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