EX128-FCS128 데이터 시트보기 (PDF) - Actel Corporation
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EX128-FCS128 Datasheet PDF : 36 Pages
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eX Family FPGAs
eX Family Timing Characteristics (Continued)
(Worst-Case Commercial Conditions VCCA = 2.3V, VCCI = 4.75V, TJ = 70°C)
‘–P’ Speed
‘Std’ Speed
‘–F’ Speed
Parameter Description
Min. Max. Min. Max. Min. Max. Units
Dedicated (Hard-Wired) Array Clock Networks
tHCKH
Input LOW to HIGH
(Pad to R-Cell Input)
tHCKL
Input HIGH to LOW
(Pad to R-Cell Input)
tHPWH
Minimum Pulse Width HIGH
tHPWL
Minimum Pulse Width LOW
tHCKSW
Maximum Skew
tHP
Minimum Period
fHMAX
Maximum Frequency
Routed Array Clock Networks
1.1
1.6
2.3
ns
1.1
1.6
2.3
ns
1.4
2.0
2.8
ns
1.4
2.0
2.8
ns
<0.1
<0.1
<0.1 ns
2.8
4.0
5.6
ns
357
250
178 MHz
tRCKH
Input LOW to HIGH (Light Load)
(Pad to R-Cell Input) MAX.
1.1
1.6
2.2
ns
tRCKL
Input HIGH to LOW (Light Load)
(Pad to R-Cell Input) MAX.
1.0
1.4
2.0
ns
tRCKH
Input LOW to HIGH (50% Load)
(Pad to R-Cell Input) MAX.
1.2
1.7
2.4
ns
tRCKL
Input HIGH to LOW (50% Load)
(Pad to R-Cell Input) MAX.
1.2
1.7
2.4
ns
tRCKH
Input LOW to HIGH (100% Load)
(Pad to R-Cell Input) MAX.
1.3
1.9
2.6
ns
tRCKL
Input HIGH to LOW (100% Load)
(Pad to R-Cell Input) MAX.
1.3
1.9
2.6
ns
tRPWH
Min. Pulse Width HIGH
1.5
2.1
3.0
ns
tRPWL
tRCKSW1
tRCKSW1
tRCKSW1
Min. Pulse Width LOW
Maximum Skew (Light Load)
Maximum Skew (50% Load)
Maximum Skew (100% Load)
1.5
2.1
3.0
ns
0.2
0.3
0.4
ns
0.1
0.2
0.3
ns
0.1
0.1
0.2
ns
Note:
1. Clock skew improves as the clock network becomes more heavily loaded.
v3.0
17
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