EX128-FCS128 데이터 시트보기 (PDF) - Actel Corporation

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EX128-FCS128

ex Family FPGAs

Actel Corporation 

eX Family FPGAs

eX Timing Model*

Input Delays

I/O Module

tINYH= 0.7 ns

tIRD1 = 0.3 ns

tIRD2 = 0.4 ns

Internal Delays

Combinatorial

Cell

Predicted

Routing

Delays

Output Delays

I/O Module

Routed

Clock

Hard-Wired

Clock

t

t

SUD = 0.5 ns

HD = 0.0 ns

tPD = 0.7 ns

Register

Cell

tttRRRDDD841

=

=

=

0.3

0.7

1.2

ns

ns

ns

tDHL = 2.6 ns

I/O Module

DQ

tRD1 = 0.3 ns

tENZL= 1.9 ns

tDHL = 2.6 ns

tRCKH= 1.3 ns

(100% Load)

I/O Module

tINYH= 0.7 ns

tIRD1 = 0.3 ns

ttSHUDD==00.0.5nnss

tRCO= 0.6 ns

Register

Cell

DQ

tRD1 = 0.3 ns

I/O Module

tENZL= 1.9 ns

tDHL = 2.6 ns

tHCKH= 1.1 ns

tRCO= 0.6 ns

*Values shown for eX128–P, worst-case commercial conditions (5.0V, 35pF Pad Load).

Hard-Wired Clock

External Setup = tINYH + tIRD1 + tSUD – tHCKH

= 0.7 + 0.3 + 0.5 – 1.1 = 0.4 ns

Clock-to-Out (Pad-to-Pad), typical

= tHCKH + tRCO + tRD1 + tDHL

= 1.1 + 0.6 + 0.3 + 2.6 = 4.6 ns

Routed Clock

External Setup = tINYH + tIRD2 + tSUD – tRCKH

= 0.7 + 0.4 + 0.5 – 1.3= 0.3 ns

Clock-to-Out (Pad-to-Pad), typical

= tRCKH + tRCO + tRD1 + tDHL

= 1.3+ 0.6 + 0.3 + 2.6 = 4.8 ns

v3.0

13

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