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LTC1283ACN

3V Single Chip 10-Bit Data Acquisition System

Linear Technology 

LTC1283

TYPICAL PERFOR A CE CHARACTERISTICS

Sample-and-Hold Acquisition

Time vs Source Resistance

10

9

8

7

6

VCC = 3V

VREF = 2.5V

TA = 25°C

0V TO 2.5V INPUT STEP

5

4

RSOURCE+

VIN

+

3

–

2

Input Channel Leakage Current

vs Temperature

1000

100

VCC = 3V

VREF = 2.5V

GUARANTEED

10

ON

CHANNEL

1

OFF

CHANNEL

0.1

1

0.01

0.1

1

10

–50 –25 0 25 50 75 100 125

RSOURCE (kΩ)

AMBIENT TEMPERATURE (°C)

LTC1283 • G13

LTC1283 • G14

Noise Error

vs Reference Voltage

1.2

VCC = 3V

ACLK = 500kHz

1.0

0.8

LTC1283 NOISE = 200µVP-P

0.6

0.4

0.2

0

0

0.5

1.0

1.5

2.0

2.5

REFERENCE VOLTAGE (V)

LTC1283 • G15

PI FU CTIO S

#

PIN

1-8

CH0-CH7

9

COM

FUNCTION

Analog Inputs

Common

10

11

12

13, 14

15

16

17

18

19

20

DGND

AGND

V–

REF –, REF +

CS

DOUT

DIN

SCLK

ACLK

VCC

Digital Ground

Analog Ground

Negative Supply

Reference Inputs

Chip Select Input

Digital Data Output

Data Input

Shift Clock

A/D Conversion Clock

Positive Supply

DESCRIPTION

The analog inputs must be free of noise with respect to AGND.

The common pin defines the zero reference point for all single-ended inputs. It must be

free of noise and is usually tied to the analog ground plane.

This is the ground for the internal logic. Tie to the ground plane.

AGND should be tied directly to the analog ground plane.

Tie V – to most negative potential in the circuit. (Ground in single supply applications.)

The reference inputs must be kept free of noise with respect to AGND.

A logic low on this input enables data transfer.

The A/D conversion result is shifted out of this output.

The A/D configuration word is shifted into this input.

This clock synchronizes the serial data transfer.

This clock controls the A/D conversion process.

This supply must be kept free of noise and ripple by bypassing directly to the analog

ground plane.

BLOCK DIAGRA

VCC 20

17

DIN

INPUT

SHIFT

REGISTER

CH0 1

CH1 2

3

CH2

CH3 4

CH4 5

CH5 6

7

CH6

CH7 8

COM 9

ANALOG

INPUT MUX

10

DGND

11

AGND

6

SAMPLE-

AND-

HOLD

COMP

10-BIT

CAPACITIVE

DAC

12

13

V–

REF–

14

REF+

OUTPUT

SHIFT

REGISTER

18

SCLK

16

DOUT

10-BIT

SAR

CONTROL

AND

TIMING

19

ACLK

15

CS

LTC1283 BD

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