DS80C411-FNY 데이터 시트보기 (PDF) - Maxim Integrated
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DS80C411-FNY Datasheet PDF : 102 Pages
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EXTERNAL CLOCK OSCILLATOR (XTAL1) CHARACTERISTICS
PARAMETER
Clock Oscillator Period
Clock Symmetry at 0.5 x VCC3
Clock Rise Time
Clock Fall Time
SYMBOL
tCLK
tCH
tCR
tCF
MIN
MAX
See External Clock
Oscillator Frequency
0.45 tCLK
0.55 tCLK
3
3
EXTERNAL CLOCK DRIVE
tCF
tCR
XTAL1
tCH
tCL
tCLK
UNITS
ns
ns
ns
SYSTEM CLOCK TIME PERIODS (tCLCL, tCHCL, tCLCH)
SYSTEM CLOCK SELECTION
4X/2X
CD1
CD0
SYSTEM CLOCK
PERIOD tCLCL
SYSTEM CLOCK HIGH (tCHCL ) AND
SYSTEM CLOCK LOW (tCLCH)
MIN
MAX
1
0
0
0
0
0
X
1
0
X
1
1
tCLK / 4
tCLK / 2
tCLK
256 tCLK
0.45 (tCLK / 4)
0.45 (tCLK / 2)
0.45 tCLK
0.45 (256 tCLK)
0.55 (tCLK / 4)
0.55 (tCLK / 2)
0.55 tCLK
0.55 (256 tCLK)
Note 1: Figure 21 shows a detailed description and illustration of the system clock selection.
Note 2: When an external clock oscillator is used in conjunction with the default system clock selection (CD1:CD0 = 10b), the
minimum/maximum system clock high (tCHCL) and system clock low (tCLCH) periods are directly related to clock oscillator duty cycle.
MOVX CHARACTERISTICS (MULTIPLEXED ADDRESS/DATA BUS) (Note 1)
(VCC3 = 3.0V to 3.6V, VCC1 = 1.8V ±10%, TA = -40 °C to +85°C.)
PARAMETER
SYMBOL
MIN
MAX
MOVX ALE Pulse Width
tLHLL2
Port 0 MOVX Address Valid
to ALE Low
tAVLL2
Port 0 MOVX Address Hold
after ALE Low
RD Pulse Width (P3.7 or
PSEN)
WR Pulse Width (P3.6)
RD (P3.7 or PSEN) Low to
Valid Data In
Data Hold After RD (P3.7 or
PSEN) High
Data Float After RD (P3.7 or
tLLAX2
and tLLAX3
tRLRH
tWLWH
tRLDV
tRHDX
tRHDZ
tCLCL + tCHCL - 5
2tCLCL - 5
6tCLCL - 5
tCHCL - 5
tCLCL - 6
5tCLCL - 6
tCLCH - 2
tCLCL - 2
5tCLCL - 2
2tCLCL - 5
(4 x CST) tCLCL - 3
2tCLCL - 5
(4 x CST) tCLCL - 3
-2
2tCLCL - 18
(4 x CST) tCLCL - 18
tCLCL - 5
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
STRETCH VALUES
CST (MD2:0)
CST = 0
1≤ CST ≤ 3
4 ≤ CST ≤ 7
CST = 0
1≤ CST ≤ 3
4 ≤ CST ≤ 7
CST = 0
1≤ CST ≤3
4 ≤ CST ≤ 7
CST = 0
1 ≤ CST ≤ 7
CST = 0
1 ≤ CST ≤ 7
CST = 0
1 ≤ CST ≤ 7
CST = 0
5 of 102
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