DS1881E-045TR 데이터 시트보기 (PDF) - Maxim Integrated

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DS1881E-045TR

Dual NV Audio Taper Digital Potentiometer

Maxim Integrated 

Dual NV Audio Taper Digital Potentiometer

setup time (see Figure 4) before the next rising edge of

SCL during a bit read. The device shifts out each bit of

data on SDA at the falling edge of the previous SCL

pulse and the data bit is valid at the rising edge of the

current SCL pulse. Remember that the master gener-

ates all SCL clock pulses including when it is reading

bits from the slave.

Acknowledgement (ACK and NACK): An Acknowledge-

ment (ACK) or Not Acknowledge (NACK) is always the

9th bit transmitted during a byte transfer. The device

receiving data (the master during a read or the slave

during a write operation) performs an ACK by transmit-

ting a zero during the 9th bit. A device performs a

NACK by transmitting a one during the 9th bit. Timing

(Figure 4) for the ACK and NACK is identical to all other

bit writes. An ACK is the acknowledgment that the

device is properly receiving data. A NACK is used to

terminate a read sequence or as an indication that the

device is not receiving data.

SDA

SCL

START

CONDITION

MSB

SLAVE ADDRESS

R/W

DIRECTION

BIT

ACKNOWLEDGEMENT

SIGNAL FROM RECEIVER

1

2

6

7

8

9

ACK

ACKNOWLEDGEMENT

SIGNAL FROM RECEIVER

1

2

3–7

8

9

ACK

REPEATED IF MORE BYTES

ARE TRANSFERRED

Figure 3. Data Transfer Protocol

STOP

CONDITION

OR REPEATED

START

CONDITION

SDA

tBUF

tLOW

tR

tF

tHD:STA

SCL

tHD:STA

STOP START

NOTE: TIMING IS REFERENCED TO VIL(MAX) AND VIH(MIN).

tHD:DAT

tHIGH

tSU:DAT

tSU:STA

REPEATED

START

Figure 4. I2C Timing Diagram

14 ____________________________________________________________________

tSP

tSU:STO

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