DS1265W 데이터 시트보기 (PDF) - Dallas Semiconductor -> Maxim Integrated
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DS1265W Datasheet PDF : 8 Pages
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POWER-DOWN/POWER-UP CONDITION
DS1265W
SEE NOTE 11
POWER-DOWN/POWER-UP TIMING
PARAMETER
SYMBOL
VCC Fail Detect to CE and WE Inactive
tPD
VCC Slew from VTP to 0V
tF
VCC Slew from 0V to VTP
tR
VCC Valid to CE and WE Inactive
tPU
VCC Valid to End of Write Protection
tREC
MIN
150
150
TYP
(TA: See Note 10)
MAX UNITS NOTES
1.5
ms
11
ms
ms
2
ms
125
ms
PARAMETER
Expected Data-Retention Time
SYMBOL MIN TYP
tDR
10
MAX
(TA = 25°C)
UNITS NOTES
years
9
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery
backup mode.
NOTES:
1. WE is high for a read cycle.
2. OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high-impedance state.
3. tWP is specified as the logical AND of CE or WE . tWP is measured from the latter of CE or WE going
low to the earlier of CE or WE going high.
4. tDS is measured from the earlier of CE or WE going high.
5. These parameters are sampled with a 5pF load and are not 100% tested.
6. If the CE low transition occurs simultaneously with or latter than the WE low transition, the output
buffers remain in a high-impedance state during this period.
7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output
buffers remain in a high-impedance state during this period.
8. If WE is low or the WE low transition occurs prior to, or simultaneously with, the CE low transition,
the output buffers remain in a high-impedance state during this period.
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