DM74LS166 데이터 시트보기 (PDF) - Fairchild Semiconductor
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DM74LS166 Datasheet PDF : 6 Pages
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Function Table
Inputs
Internal
Output
Clear Shift/ Clock Clock Serial Parallel
Outputs
QH
Load Inhibit
A…H
QA
QB
L
X
X
X
X
X
L
L
L
H
X
L
L
X
X
QA0
QB0
QH0
H
L
L
↑
X
a…h
a
b
h
H
H
L
↑
H
X
H
QAn
H
H
L
↑
L
X
L
QAn
H
X
H
↑
X
X
QA0
QB0
H = HIGH Level (steady state)
L = LOW Level (steady state)
X = Don’t Care (any input, including transitions)
↑ = Transition from LOW-to-HIGH level
a…h = The level of steady-state input at inputs A through H, respectively
QA0, QB0, QH0 = The level of QA, QB, QH, respectively, before the indicated steady-state input conditions were established
QAn, QGn, = The level of QA, QG, respectively, before the most recent ↑ transition of the clock
QGn
QGn
QH0
Logic Diagram
Timing Diagram
Typical Clear, Shift, Load, Inhibit and Shift Sequences
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