CY8C27643-24LKXI 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY8C27643-24LKXI Datasheet PDF : 63 Pages
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CY8C27143, CY8C27243
CY8C27443, CY8C27543
CY8C27643
PSoC Functional Overview
The PSoC family consists of many programmable
system-on-chip controller devices. These devices are designed
to replace multiple traditional microcontroller unit (MCU)-based
system components with one, low-cost single-chip
programmable device. PSoC devices include configurable
blocks of analog and digital logic, as well as programmable
interconnects. This architecture lets you to create customized
peripheral configurations that match the requirements of each
individual application. Additionally, a fast central processing unit
(CPU), flash program memory, SRAM data memory, and
configurable I/O are included in a range of convenient pinouts
and packages.
The PSoC architecture, as illustrated in Logic Block Diagram on
page 1, consists of four main areas: PSoC core, digital system,
analog system, and system resources. Configurable global
busing allows all the device resources to be combined into a
complete custom system. The PSoC CY8C27x43 family can
have up to five I/O ports that connect to the global digital and
analog interconnects, providing access to eight digital blocks and
12 analog blocks.
PSoC Core
The PSoC core is a powerful engine that supports a rich feature
set. The core includes a CPU, memory, clocks, and configurable
GPIO.
The M8C CPU core is a powerful processor with speeds up to
24 MHz, providing a four MIPS 8-bit Harvard architecture
microprocessor. The CPU uses an interrupt controller with 17
vectors, to simplify programming of real time embedded events.
Program execution is timed and protected using the included
sleep and watchdog timers (WDT).
Memory encompasses 16 KB of flash for program storage,
256 bytes of SRAM for data storage, and up to 2 K of EEPROM
emulated using the flash. Program flash uses four protection
levels on blocks of 64 bytes, allowing customized software IP
protection.
The PSoC device incorporates flexible internal clock generators,
including a 24-MHz internal main oscillator (IMO) accurate to
2.5% over temperature and voltage. The 24-MHz IMO can also
be doubled to 48 MHz for use by the digital system. A low power
32-kHz internal low speed oscillator (ILO) is provided for the
sleep timer and WDT. If crystal accuracy is desired, the
32.768-kHz external crystal oscillator (ECO) is available for use
as a Real Time Clock (RTC) and can optionally generate a
crystal-accurate 24-MHz system clock using a PLL. The clocks,
together with programmable clock dividers (as a system
resource), provide the flexibility to integrate almost any timing
requirement into the PSoC device.
PSoC GPIOs provide connection to the CPU, digital and analog
resources of the device. Each pin’s drive mode may be selected
from eight options, allowing great flexibility in external
interfacing. Every pin also has the capability to generate a
system interrupt on high level, low level, and change from last
read.
Digital System
The digital system is composed of eight digital PSoC blocks.
Each block is an 8-bit resource that can be used alone or
combined with other blocks to form 8-, 16-, 24-, and 32-bit
peripherals, which are called user modules.
Figure 1. Digital System Block Diagram
Port 5
Port 4
Port 3
Port 2
Port 1
Port 0
8
8
DigitalClocks To System Bus
FromCore
ToAnalog
System
DIGITAL SYSTEM
Digital PSoC Block Array
Row 0
4
DBB00
DBB01
DCB02
DCB03
4
Row 1
4
DBB10
DBB11
DCB12
DCB13
4
8
8
GIE[7:0]
GIO[7:0]
Global Digital
Interconnect
GOE[7:0]
GOO[7:0]
Digital peripheral configurations include:
■ PWMs (8- to 32-bit)
■ PWMs with dead band (8- to 32-bit)
■ Counters (8- to 32-bit)
■ Timers (8- to 32-bit)
■ UART 8-bit with selectable parity (up to two)
■ SPI slave and master (up to two)
■ I2C slave and multi-master (one available as a system
resource)
■ CRC/generator (8- to 32-bit)
■ IrDA (up to two)
■ Pseudo random sequence (PRS) generators (8- to 32-bit)
Document Number: 38-12012 Rev. *T
Page 3 of 63
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