CY7C63001A 데이터 시트보기 (PDF) - Cypress Semiconductor

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CY7C63001A

Universal Serial Bus Microcontroller

Cypress Semiconductor 

FOR

FOR

CY7C63000A/CY7C63001A

CY7C63100A/CY7C63101A

LIST OF FIGURES

Figure 5-1. Program Memory Space .................................................................................................... 7

Figure 5-2. Data Memory Space ........................................................................................................... 8

Figure 5-4. Watch Dog Reset (WDR) .................................................................................................. 10

Figure 5-3. Status and Control Register (SCR - Address 0xFF) ...................................................... 10

Figure 5-5. The Cext Register (Address 0x22) .................................................................................. 11

Figure 5-6. Timer Register (Address 0x23)........................................................................................ 11

Figure 5-7. Timer Block Diagram........................................................................................................ 11

Figure 5-8. Port 0 Data Register (Address 0x00) .............................................................................. 12

Figure 5-9. Port 1 Data Register (Address 0x01) .............................................................................. 12

Figure 5-10. Block Diagram of an I/O Line......................................................................................... 12

Figure 5-11. Port 0 Pull-up Register (Address 0x08) ........................................................................ 13

Figure 5-12. Port 1 Pull-up Register (Address 0x09) ........................................................................ 13

Figure 5-13. Port Isink Register for One GPIO Line.......................................................................... 13

Figure 5-14. Clock Oscillator On-chip Circuit ................................................................................... 14

Figure 5-16. Interrupt Controller Logic Block Diagram .................................................................... 14

Figure 5-15. Global Interrupt Enable Register (GIER - Address 0x20)............................................ 14

Figure 5-17. Port 0 Interrupt Enable Register (P0 IE - Address 0x04)............................................. 15

Figure 5-18. Port 1 Interrupt Enable Register (P1 IE - Address 0x05)............................................. 15

Figure 5-19. GPIO Interrupt Logic Block Diagram ............................................................................ 16

Figure 5-20. USB Device Address Register (USB DA - Address 0x12) ........................................... 17

Figure 5-21. USB Endpoint 0 RX Register (Address 0x14) .............................................................. 17

Figure 5-22. USB Endpoint 0 TX Configuration Register (Address 0x10) ...................................... 18

Figure 5-23. USB Endpoint 1 TX Configuration Register (Address 0x11) ...................................... 19

Figure 5-24. USB Status and Control Register (USB SCR - Address 0x13) ................................... 19

Figure 5-25. Low-speed Driver Signal Waveforms ........................................................................... 20

Figure 5-26. Differential Input Sensitivity Over Entire Common Mode Range............................... 20

Figure 5-27. Application Showing 7.5kW±1% Pull-Up Resistor....................................................... 21

Figure 5-28. Application Showing 1.5-kW±5% Pull-Up Resistor ..................................................... 21

Figure 8-1. Clock Timing ..................................................................................................................... 26

Figure 8-2. USB Data Signal Timing and Voltage Levels ................................................................. 26

Figure 8-3. Receiver Jitter Tolerance ................................................................................................. 26

Figure 8-4. Differential to EOP Transition Skew and EOP Width .................................................... 27

Figure 8-5. Differential Data Jitter ...................................................................................................... 27

LIST OF TABLES

Table 5-1. I/O Register Summary ......................................................................................................... 9

Table 5-2. Output Control Truth Table .............................................................................................. 13

Table 5-3. Interrupt Vector Assignments .......................................................................................... 15

Table 5-4. USB Engine Response to SETUP and OUT Transactions on Endpoint 0 .................... 18

Table 5-5. Instruction Set Map ........................................................................................................... 21

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Document #: 38-08026 Rev. **

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