CY7C63200 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY7C63200 Datasheet PDF : 27 Pages
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PRELIMINARY
CY7C63000/CY7C63001
CY7C63100/CY7C63101
CY7C63200/CY7C63201
3.0 Pin Definitions
Name
I/O
P0.0
I/O
P0.1
I/O
P0.2
I/O
P0.3
I/O
P0.4
I/O
P0.5
I/O
P0.6
I/O
P0.7
I/O
P1.0
I/O
P1.1
I/O
P1.2
I/O
P1.3
I/O
P1.4
I/O
P1.5
I/O
P1.6
I/O
P1.7
I/O
XTALIN
I
XTALOUT
O
CEXT
I/O
D+
I/O
D–
I/O
VPP
–
VCC
–
VSS
–
18-Pin
1
2
3
4
18
17
16
15
5
14
–
–
–
–
–
–
9
10
8
13
12
7
11
6
20-Pin
1
2
3
4
20
19
18
17
5
16
6
15
–
–
–
–
10
11
9
14
13
8
12
7
24-pin
1
2
3
4
24
23
22
21
5
20
6
19
7
18
8
17
12
13
11
16
15
10
14
9
Description
Port 0 bit 0
Port 0 bit 1
Port 0 bit 2
Port 0 bit 3
Port 0 bit 4
Port 0 bit 5
Port 0 bit 6
Port 0 bit 7
Port 1 bit 0
Port 1 bit 1
Port 1 bit 2
Port 1 bit 3
Port 1 bit 4
Port 1 bit 5
Port 1 bit 6
Port 1 bit 7
Crystal / Ceramic resonator in or external clock input
Crystal / Ceramic resonator out
Connects to external R/C timing circuit for optional suspend
wakeup
USB data+
USB data–
Programming voltage supply, tie to ground during normal
operation
Voltage supply
Ground
6
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