CY7C421-20JXI 데이터 시트보기 (PDF) - Cypress Semiconductor

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CY7C421-20JXI

512 × 9 Asynchronous FIFO

Cypress Semiconductor 

CY7C421

Pin Definitions

Signal Name Description

W

Write Signal

R

Read Signal

D0–D8

Q0–Q8

XI

Input Data

Output Data

Expansion In

XO

Expansion Out

HF

Half Full Flag

FF

Full Flag

EF

Empty Flag

MR

Master Reset

RT

Retransmit

FL

First Load

VCC

GND

Power

Ground

I/O

Function

I Write into the FIFO

I Read from the FIFO

I Data into the FIFO

O Data Out from the FIFO

I Cascaded: Connected to XO of pervious device

Non-Cascaded: Connected to VCC

O Cascaded: Connected to XI of next device

Non-Cascaded: Connected to VCC

O Half-full flag: When HF is LOW, half of the FIFO is full.

O When FF is LOW, the FIFO is full.

O When EF is LOW, the FIFO is empty.

I FIFO Reset

I Causes FIFO to retransmit the data

I Width expansion: Connected to VCC

Depth expansion: when Gnd indicates that part is first to be loaded all others connected to

VCC

I Voltage Supply

I Ground

Document Number: 38-06001 Rev. *H

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