CY7C1481V33-100AXC 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY7C1481V33-100AXC Datasheet PDF : 30 Pages
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CY7C1481V33
CY7C1483V33
CY7C1487V33
Truth Table
The truth table for CY7C1481V33, CY7C1483V33, and CY7C1487V33 follows.[3, 4, 5, 6, 7]
Cycle Description
ADDRESS
Used
CE1
CE2
CE3
ZZ
Deselected Cycle,
Power Down
None
H X XL
Deselected Cycle,
Power Down
None
L L XL
Deselected Cycle,
Power Down
None
L X HL
Deselected Cycle,
Power Down
None
L L XL
Deselected Cycle,
Power Down
None
X X XL
Sleep Mode, Power Down
None
X X XH
Read Cycle, Begin Burst
External L H L L
Read Cycle, Begin Burst
External L H L L
Write Cycle, Begin Burst
External L H L L
Read Cycle, Begin Burst
External L H L L
Read Cycle, Begin Burst
External L H L L
Read Cycle, Continue Burst Next
X X XL
Read Cycle, Continue Burst Next
X X XL
Read Cycle, Continue Burst Next
H X XL
Read Cycle, Continue Burst Next
H X XL
Write Cycle, Continue Burst Next
X X XL
Write Cycle, Continue Burst Next
H X XL
Read Cycle, Suspend Burst Current X X X L
Read Cycle, Suspend Burst Current X X X L
Read Cycle, Suspend Burst Current H X X L
Read Cycle, Suspend Burst Current H X X L
Write Cycle, Suspend Burst Current X X X L
Write Cycle, Suspend Burst Current H X X L
ADSP
X
L
L
H
H
X
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
ADSC ADV WRITE OE CLK DQ
L
X
X
X L-H Tri-State
X
X
X
X L-H Tri-State
X
X
X
X L-H Tri-State
L
X
X
X L-H Tri-State
L
X
X
X L-H Tri-State
X
X
X
X X Tri-State
X
X
X
L L-H
Q
X
X
X
H L-H Tri-State
L
X
L
X L-H
D
L
X
H
L L-H
Q
L
X
H
H L-H Tri-State
H
L
H
L L-H
Q
H
L
H
H L-H Tri-State
H
L
H
L L-H
Q
H
L
H
H L-H Tri-State
H
L
L
X L-H
D
H
L
L
X L-H
D
H
H
H
L L-H
Q
H
H
H
H L-H Tri-State
H
H
H
L L-H
Q
H
H
H
H L-H Tri-State
H
H
L
X L-H
D
H
H
L
X L-H
D
Notes
3. X = Do Not Care, H = Logic HIGH, L = Logic LOW.
4. WRITE = L when any one or more Byte Write Enable signals and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals, BWE, GW = H.
5. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after
the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to enable the outputs to tri-state. OE is a do not
care for the remainder of the write cycle.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is
inactive or when the device is deselected, and all data bits behave as outputs when OE is active (LOW).
Document #: 38-05284 Rev. *H
Page 10 of 30
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