CY7C1350G(2004) 데이터 시트보기 (PDF) - Cypress Semiconductor
부품명
상세내역
제조사
CY7C1350G Datasheet PDF : 15 Pages
| |||
PRELIMINARY
CY7C1350G
Electrical Characteristics Over the Operating Range (continued)[10, 11]
Parameter
Description
Test Conditions
ISB3
Automatic CE
VDD = Max, Device Deselected, or 4-ns cycle, 250 MHz
Power-Down
VIN ≤ 0.3V or VIN > VDDQ – 0.3V 4.4-ns cycle, 225 MHz
Current—CMOS Inputs f = fMAX = 1/tCYC
5-ns cycle, 200 MHz
6-ns cycle, 166 MHz
7.5-ns cycle, 133 MHz
10-ns cycle, 100 MHz
ISB4
Automatic CE
VDD = Max, Device Deselected, All speeds
Power-Down
VIN ≥ VIH or VIN ≤ VIL, f = 0
Current—TTL Inputs
Min.
Max. Unit
105
mA
100
mA
95
mA
85
mA
75
mA
65
mA
45
mA
AC Test Loads and Waveforms
3.3V I/O Test Load
OUTPUT
Z0 = 50Ω
3.3V
OUTPUT
RL = 50Ω
5 pF
VT = 1.5V
(a)
2.5V I/O Test Load
INCLUDING
JIG AND
SCOPE
R = 317Ω
R = 351Ω
(b)
VDDQ
GND
ALL INPUT PULSES
10%
90%
≤ 1 ns
90%
10%
≤ 1 ns
(c)
OUTPUT
Z0 = 50Ω
2.5V
OUTPUT
RL = 50Ω
5 pF
VT = 1.25V
(a)
INCLUDING
JIG AND
SCOPE
R = 1667Ω
R =1538Ω
VDDQ
GND
ALL INPUT PULSES
10%
90%
≤ 1 ns
90%
10%
≤ 1 ns
(b)
(c)
Thermal Resistance[12]
Parameter
Description
Test Conditions
ΘJA
Thermal Resistance Test conditions follow standard test methods
(Junction to Ambient) and procedures for measuring thermal
ΘJC
Thermal Resistance impedance, per EIA/JESD51.
(Junction to Case)
TQFP Package
TBD
TBD
BGA Package Unit
TBD
°C/W
TBD
°C/W
Capacitance[12]
Parameter
Description
Test Conditions
CIN
CCLK
Input Capacitance
Clock Input Capacitance
TA = 25°C, f = 1 MHz,
VDD = 3.3V, VDDQ = 3.3V
CI/O
Input/Output Capacitance
Note:
12. Tested initially and after any design or process changes that may affect these parameters.
TQFP Package
5
5
5
BGA Package
5
5
7
Unit
pF
pF
pF
Document #: 38-05524 Rev. *A
Page 8 of 15
Share Link: 