CY7C1350G(2004) 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY7C1350G Datasheet PDF : 15 Pages
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PRELIMINARY
CY7C1350G
DQP[A:D]. In addition, the address for the subsequent access
(Read/Write/Deselect) is latched into the Address Register
(provided the appropriate control signals are asserted).
On the next clock rise the data presented to DQs and DQP[A:D]
(or a subset for Byte Write operations, see Write Cycle
Description table for details) inputs is latched into the device
and the write is complete.
The data written during the Write operation is controlled by
BW[A:D] signals. The CY7C1350G provides byte write
capability that is described in the Write Cycle Description table.
Asserting the Write Enable input (WE) with the selected Byte
Write Select (BW[A:D]) input will selectively write to only the
desired bytes. Bytes not selected during a Byte Write
operation will remain unaltered. A synchronous self-timed
write mechanism has been provided to simplify the write
operations. Byte write capability has been included in order to
greatly simplify Read/Modify/Write sequences, which can be
reduced to simple byte write operations.
Because the CY7C1350G is a common I/O device, data
should not be driven into the device while the outputs are
active. The Output Enable (OE) can be deasserted HIGH
before presenting data to the DQs and DQP[A:D] inputs. Doing
so will tri-state the output drivers. As a safety precaution, DQs
and DQP[A:D] are automatically tri-stated during the data
portion of a write cycle, regardless of the state of OE.
Burst Write Accesses
The CY7C1350G has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Write operations without reasserting the address inputs.
ADV/LD must be driven LOW in order to load the initial
address, as described in the Single Write Access section
above. When ADV/LD is driven HIGH on the subsequent clock
rise, the chip enables (CE1, CE2, and CE3) and WE inputs are
ignored and the burst counter is incremented. The correct
Truth Table [2, 3, 4, 5, 6, 7, 8]
BW[A:D] inputs must be driven in each cycle of the burst write
in order to write the correct bytes of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE1, CE2, and CE3, must remain inactive
for the duration of tZZREC after the ZZ input returns LOW.
Interleaved Burst Address Table
(MODE = Floating or VDD)
First Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Linear Burst Address Table (MODE = GND)
First Address
A1, A0
00
01
10
11
Second
Address
A1, A0
01
10
11
00
Third
Address
A1, A0
10
11
00
01
Fourth
Address
A1, A0
11
00
01
10
Operation
Deselect Cycle
Address Used
None
CE ZZ ADV/LD WE BWx OE CEN CLK
DQ
HL
L
X X X L L-H tri-state
Continue Deselect Cycle
None
XL
H
X X X L L-H tri-state
Read Cycle (Begin Burst)
External
LL
L
H X L L L-H Data Out (Q)
Read Cycle (Continue Burst)
Next
XL
H
X X L L L-H Data Out (Q)
NOP/Dummy Read (Begin Burst) External
LL
L
H X H L L-H tri-state
Dummy Read (Continue Burst) Next
XL
H
X X H L L-H tri-state
Write Cycle (Begin Burst)
External
LL
L
L L X L L-H Data In (D)
Write Cycle (Continue Burst)
Next
XL
H
X L X L L-H Data In (D)
NOP/WRITE ABORT (Begin Burst) None
LL
L
L H X L L-H tri-state
WRITE ABORT (Continue Burst) Next
XL
H
X H X L L-H tri-state
IGNORE CLOCK EDGE (Stall) Current
XL
X
X X X H L-H —
SNOOZE MODE
None
XH
X
X X X X X tri-state
Notes:
2.
X =”Don't Care.” H = Logic HIGH, L = Logic
signifies that the desired byte write selects
LOW. CE stands for ALL Chip
are asserted, see Write Cycle
EDneasbclreipstiaocntivtaeb.lBeWfoxr
= L signifies
details.
at
least
one Byte
Write Select
is
active,
BWx
=
Valid
3. Write is defined by BWX, and WE. See Write Cycle Descriptions table.
4. When a write cycle is detected, all DQs are tri-stated, even during byte writes.
5. The DQ and DQP pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. CEN = H, inserts wait states.
7. Device will power-up deselected and the DQs in a tri-state condition, regardless of OE.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP[A:D] = tri-state when
OE is inactive or when the device is deselected, and DQs and DQP[A:D] = data when OE is active.
Document #: 38-05524 Rev. *A
Page 5 of 15
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