CY7C1325H 데이터 시트보기 (PDF) - Cypress Semiconductor

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CY7C1325H

4-Mbit (256 K × 18) Flow-Through Sync SRAM

Cypress Semiconductor 

Timing Diagrams (continued)

Figure 6. ZZ Mode Timing [22, 23]

CY7C1325H

CLK

ZZ

I SUPPLY

A LL INPUTS

(except ZZ)

Outputs (Q)

t ZZ

t ZZI

I DDZZ

t ZZREC

High-Z

DON’T CARE

t RZZI

DESELECT or READ Only

Notes

22. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.

23. DQs are in High Z when exiting ZZ sleep mode.

Document Number: 001-86114 Rev. **

Page 16 of 21

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