CY7C1325G-133BGI 데이터 시트보기 (PDF) - Cypress Semiconductor

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CY7C1325G-133BGI

4-Mbit (256K x 18) Flow-Through Sync SRAM

Cypress Semiconductor 

CY7C1325G

Timing Diagrams (continued)

Write Cycle Timing[16, 17]

tCYC

CLK

ADSP

ADSC

ADDRESS

BWE,

BW[A:B]

GW

CE

ADV

t

CH

t CL

tADS tADH

tADS tADH

tAS tAH

A1

A2

Byte write signals are ignored for first cycle when

ADSP initiates burst

tCES tCEH

t

t

WES WEH

ADSC extends burst

tADS tADH

A3

tWES tWEH

ADV suspends burst

tADVS tADVH

OE

tDS t DH

Data in (D)

Data Out (Q)

High-Z

D(A1)

tOEHZ

BURST READ

Single WRITE

D(A2)

D(A2 + 1)

D(A2 + 1)

D(A2 + 2)

D(A2 + 3)

BURST WRITE

DON’T CARE

UNDEFINED

Note:

17. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW[A:B] LOW.

D(A3)

D(A3 + 1)

D(A3 + 2)

Extended BURST WRITE

Document #: 38-05518 Rev. *D

Page 11 of 16

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