CY7C1325G-133AXI(2004) 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY7C1325G-133AXI Datasheet PDF : 16 Pages
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PRELIMINARY
CY7C1325G
Switching Characteristics Over the Operating Range (continued)[14, 15]
Parameter
tCHZ
tOEV
tOELZ
tOEHZ
Setup Times
tAS
tADS
tADVS
tWES
tDS
tCES
Hold Times
tAH
tADH
tWEH
tADVH
tDH
tCEH
Description
Clock to High-Z[11, 12, 13]
OE LOW to Output Valid
OE LOW to Output Low-Z[11, 12, 13]
OE HIGH to Output High-Z[11, 12, 13]
Address Set-up Before CLK Rise
ADSP, ADSC Set-up Before CLK Rise
ADV Set-up Before CLK Rise
GW, BWE, BWX Set-up Before CLK Rise
Data Input Set-up Before CLK Rise
Chip Enable Set-up
Address Hold After CLK Rise
ADSP, ADSC Hold After CLK Rise
GW,BWE, BWX Hold After CLK Rise
ADV Hold After CLK Rise
Data Input Hold After CLK Rise
Chip Enable Hold After CLK Rise
133 MHz
117 MHz
100 MHz
Min. Max. Min. Max. Min. Max. Unit
3.5
3.5
3.5 ns
3.5
3.5
3.5 ns
0
0
0
ns
3.5
3.5
3.5 ns
1.5
2.0
2.0
ns
1.5
2.0
2.0
ns
1.5
2.0
2.0
ns
1.5
2.0
2.0
ns
1.5
2.0
2.0
ns
1.5
2.0
2.0
ns
0.5
0.5
0.5
ns
0.5
0.5
0.5
ns
0.5
0.5
0.5
ns
0.5
0.5
0.5
ns
0.5
0.5
0.5
ns
0.5
0.5
0.5
ns
Document #: 38-05518 Rev. *A
Page 9 of 16
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