CY7C1021D-10VXI 데이터 시트보기 (PDF) - Cypress Semiconductor

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CY7C1021D-10VXI

1-Mbit (64K x 16) Static RAM

Cypress Semiconductor 

CY7C1021D

Data Retention Characteristics (Over the Operating Range)

Parameter

Description

Conditions

Min Max Unit

VDR

ICCDR

tCDR [4]

tR [13]

VCC for Data Retention

Data Retention Current

2.0

V

VCC = VDR = 2.0 V, CE > VCC – 0.3 V, Industrial

VIN > VCC – 0.3 V or VIN < 0.3 V

Automotive

3 mA

15 mA

Chip Deselect to Data Retention Time

0

ns

Operation Recovery Time

tRC

ns

Data Retention Waveform

DATA RETENTION MODE

VCC

4.5V

VDR > 2V

4.5V

tCDR

tR

CE

Switching Waveforms

Read Cycle No. 1 (Address Transition Controlled) [14, 15]

tRRCC

ADDRESS

DATA OUT

tAA

tOHA

PREVIOUS DATA VALID

Read Cycle No. 2 (OE Controlled) [15, 16]

ADDRESS

tRC

CE

OE

BHE, BLE

DATA OUT

VCC

SUPPLY

CURRENT

tACE

tDOE

tLZOE

tDBE

tLZBE

HIGH IMPEDANCE

tLZCE

tPU

50%

DATA VALID

tHZOE

DATA VALID

tHZCE

tHZBE

HIGH

IMPEDANCE

tPD

ICC

50%

ISB

Notes

13. Full device operation requires linear VCC ramp from VDR to VCC(min) > 50 µs or stable at VCC(min) > 50 µs.

14. Device is continuously selected. OE, CE, BHE and/or BLE = VIL.

15. WE is HIGH for read cycle.

16. Address valid prior to or coincident with CE transition LOW.

Document #: 38-05462 Rev. *E

Page 6 of 11

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