CY14B256KA(2009) 데이터 시트보기 (PDF) - Cypress Semiconductor

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CY14B256KA
(Rev.:2009)

256 Kbit (32K x 8) nvSRAM with Real Time Clock

Cypress Semiconductor 

CY14B256KA

Figure 8. SRAM Read Cycle #2: CE and OE Controlled [12, 16]

Address

CE

OE

Data Output

ICC

Address Valid

tRC

tACE

tHZCE

tAA

tLZCE

tDOE

tHZOE

High Impedance

Standby

tLZOE

tPU

Active

Output Data Valid

tPD

Figure 9. SRAM Write Cycle #1: WE Controlled [15, 16, 17]

Address

tWC

Address Valid

tSCE

tHA

CE

tAW

tPWE

WE

Data Input

Data Output

tSA

Previous Data

tHZWE

tSD

tHD

Input Data Valid

tLZWE

High Impedance

Address

CE

WE

Data Input

Data Output

Figure 10. SRAM Write Cycle #2: CE Controlled [15, 16, 17]

tWC

Address Valid

tSA

tSCE

tHA

tPWE

tSD

tHD

Input Data Valid

High Impedance

Note

17. CE or WE must be >VIH during address transitions.

Document #: 001-55720 Rev. *A

Page 19 of 26

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