CY14B101Q1-SFXI 데이터 시트보기 (PDF) - Cypress Semiconductor

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CY14B101Q1-SFXI

1-Mbit (128 K × 8) Serial SPI nvSRAM

Cypress Semiconductor 

CY14B101Q1

CY14B101Q2

CY14B101Q3

AC Switching Characteristics

Over the Operating Range[10]

Cypress

Parameter

fSCK

tCL

tCH

tCS

tCSS

tCSH

tSD

tHD

tHH

tSH

tCO

tHHZ[11]

tHLZ[11]

tOH

tHZCS

fSCK

tWL

tWH

tCE

tCES

tCEH

tSU

tH

tHD

tCD

tV

tHZ

tLZ

tHO

tDIS

Alt.

Parameter

Description

Clock frequency, SCK

Clock pulse width LOW

Clock pulse width HIGH

CS HIGH time

CS setup time

CS hold time

Data in setup time

Data in hold time

HOLD hold time

HOLD setup time

Output valid

HOLD to output High Z

HOLD to output Low Z

Output hold time

Output disable time

Switching Waveforms

Figure 21. Synchronous Data Timing (Mode 0)

CS

SCK

SI

tCSS

tCH

tSD tHD

VALID IN

HI-Z

SO

CS

tCL

VALID IN

VALID IN

tCO

Figure 22. HOLD Timing

40 MHz

Min

Max

–

40

11

–

11

–

20

–

10

–

10

–

5

–

5

–

5

–

5

–

–

9

–

15

–

15

0

–

–

25

Unit

MHz

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

tCS

tCSH

tOH

tHZCS

HI-Z

SCK

HOLD

tHH

tSH

tHHZ

tHH

tSH

tHLZ

SO

Notes

10. Test conditions assume signal transition time of 3 ns or less, timing reference levels of VCC/2, input pulse levels of 0 to VCC (Typ), and output loading of the specified

IOL/IOH and load capacitance shown in Figure 20.

11. These parameters are guaranteed by design and are not tested.

Document Number: 001-50091 Rev. *L

Page 17 of 27

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