CY14B101K-SP25XC 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY14B101K-SP25XC Datasheet PDF : 24 Pages
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Table 1. Mode Selection
CE
WE
H
X
L
H
L
L
L
H
L
H
L
H
L
H
CY14B101K
OE
A15 – A0
Mode
IO
Power
X
X
Not Selected Output High Z
Standby
L
X
READ SRAM Output Data
Active
X
X
WRITE SRAM Input Data
Active
L
0x4E38
READ SRAM Output Data
Active[1, 2, 3]
0xB1C7
READ SRAM Output Data
0x83E0
READ SRAM Output Data
0x7C1F
READ SRAM Output Data
0x703F
READ SRAM Output Data
0x8B45
AutoStore
Output Data
Disable
L
0x4E38
READ SRAM Output Data
Active[1, 2, 3]
0xB1C7
READ SRAM Output Data
0x83E0
READ SRAM Output Data
0x7C1F
READ SRAM Output Data
0x703F
Read SRAM Output Data
0x4B46
AutoStore
Output Data
Enable
L
0x4E38
Read SRAM
Output Data Active ICC2[1, 2, 3]
0xB1C7
Read SRAM Output Data
0x83E0
Read SRAM Output Data
0x7C1F
Read SRAM Output Data
0x703F
Read SRAM Output Data
0x8FC0
Nonvolatile Output High Z
Store
L
0x4E38
Read SRAM
Output Data
Active[1, 2, 3]
0xB1C7
Read SRAM Output Data
0x83E0
Read SRAM Output Data
0x7C1F
Read SRAM Output Data
0x703F
Read SRAM Output Data
0x4C63
Nonvolatile Output High Z
Recall
Notes
1. The six consecutive address locations are in the order listed. WE is HIGH during all six cycles to enable a nonvolatile cycle.
2. While there are 17 address lines on the CY14B101K, only the lower 16 lines are used to control software modes.
3. O state depends on the state of OE. The IO table shown is based on OE Low.
Document Number: 001-06401 Rev. *G
Page 5 of 24
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