Timing Charts (RAM)
(1) Write mode (XR/W = H)
XWR
A0 to 9
TWR
TCWR
TSWR
THWR
CXA2108Q
D0 to 9
Note) The address is not latched internally, so do not change the address while XWR is low.
(1) Read mode (XR/W = L)
TRD
XRD
TCRD
TSRD
THRD
A0 to 9
TPDD
D0 to 9
Note) The address is not latched internally, so do not change the address while XRD is low.
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