CS5151 데이터 시트보기 (PDF) - ON Semiconductor

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CS5151

CPU 4−Bit Nonsynchronous Buck Controller

ON Semiconductor 

CS5151

VCC1

SS

VID0

VID1

VID2

VID3

VFB

COMP

VFFB

LGND

VCC1 Monitor

− Comparator

+

3.90 V

3.85V

5.0 V

60 μA

2.0 μA

4 BIT

DAC

Error

Amplifier

+

−

Slow Feedback

PWM

Comparator

−

+

2.5 V

Fast Feedback

1.0 V

−

+

VFFB Low

Comparator

−

+

0.7 V

+

−

SS Low

Comparator

SS High

Comparator

Maximum

On−Time

Timeout

Normal

Off−Time

Timeout

Extended

Off−Time

Timeout

FAULT

RQ

S Q FAULT

FAULT

Latch

RQ

SQ

PMW

Latch

Off−Time

Timeout

GATE = ON

GATE = OFF

COFF

One Shot

R

SQ

PWM COMP

Time−Out

Timer

(30 μs)

Edge Triggered

VCC2

VGATE

PGND

COFF

Figure 2. Block Diagram

APPLICATIONS INFORMATION

THEORY OF OPERATION

V2 Control Method

The V2 method of control uses a ramp signal that is

generated by the ESR of the output capacitors. This ramp is

proportional to the AC current through the main inductor

and is offset by the value of the DC output voltage. This

control scheme inherently compensates for variation in

either line or load conditions, since the ramp signal is

generated from the output voltage itself. This control

scheme differs from traditional techniques such as voltage

mode, which generates an artificial ramp, and current mode,

which generates a ramp from inductor current.

COMP

PWM

Comparator

+

VGATE

C

−

Ramp

Signal

VFFB

Error

Signal

Error

Amplifier −

E

+

Output

Voltage

Feedback

VFB

Reference

Voltage

Figure 3. V2 Control Diagram

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