MAX121CWE 데이터 시트보기 (PDF) - Maxim Integrated

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MAX121CWE

308ksps ADC with DSP Interface and 78dB SINAD

Maxim Integrated 

MAX121

308ksps ADC with DSP Interface and 78dB SINAD

Mode 2: CS Controls Conversion Starts

(MODE = VDD, CONVST = DGND)

Figure 8 shows the timing diagram for mode 2. In mode

2, CS controls the conversion start and enables the serial

output pins. Mode 2 is useful in applications where the

MAX121 shares the output data bus with other devices.

When CS is driven high, the MAX121 is disabled and its

serial outputs (SCLK, SDATA, SFRM, and FSTRT) are

placed into a high-impedance state.

A falling edge on the CS input places the T/H into the hold

mode and starts a conversion in the SAR. The FSTRT

and SFRM outputs can be used to frame the output data

as described in the mode 1 section. CS must remain low

for the duration of the conversion.

The T/H amplifier returns to the track mode when the 14th

bit (D0) is clocked out of the SDATA pin. A new conversion

can be initiated by the CS input after the 400ns acquisition

time has been satisfied.

Mode 3: Continuous-Conversion Mode

(CONVST = CS = MODE = DGND)

For applications that do not require precise control of

sampling in time, such as data logging, the MAX121 can

operate in continuous-conversion mode, directly linked to

memory through DMA ports or a FIFO buffer.

In this mode, conversions are performed continuously

at the rate of one conversion for every 16 clock cycles,

which includes 2 clock cycles for the T/H acquisition time.

To satisfy the 400ns minimum acquisition-time require-

ment within 2 clock cycles, the MAX121 ‘s maximum clock

frequency is limited to 5MHz when operating in mode 3.

The FSTRT output is used to frame data, as described

in the mode 1 section and the mode 3 timing diagram

(Figure 9). The SFRM output is meaningless in mode 3,

since it will not change state.

The MODE input should be hardwired to DGND, since

this input must be low when the MAX121 powers up

for proper operation of mode 3. To disable conversions,

drive CONVST high. To put the serial outputs into a high-

impedance state, drive CS high.

CS

CLKIN

1

13

14

15

16*

17*

SFRM

HIGH

(INVFRM = VDC) IMPENDANCE

FSTRT

HIGH

IMPENDANCE

HIGH

IMPENDANCE

HIGH

IMPENDANCE

SCLK

HIGH

(INVCLK = VDC) IMPENDANCE

SDATA

HIGH

IMPENDANCE

HOLD

T/H

tAP

1

13

14

15

16*

17* HIGH

IMPENDANCE

tCD

MSB D2

D1

LSB

HIGH

IMPENDANCE

* THESE CLOCK CYCLES MAY BE OMITTED IF THE SFRM SIGNAL IS NOT NEEDED

Figure 8. CS Controls Conversion Starts (Mode 2)

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