MAX3890ECB 데이터 시트보기 (PDF) - Maxim Integrated
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MAX3890ECB
Maxim Integrated
MAX3890ECB Datasheet PDF : 12 Pages
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+3.3V, 2.5Gbps, SDH/SONET 16:1 Serializer
with Clock Synthesis and LVDS Inputs
PCLKO
tSKEW
PCLKI
tSU
tH
PARALLEL
INPUT DATA
(PDI_)
VALID PARALLEL DATA*
SERIAL
OUTPUT DATA
(SDO)
NOTE: SIGNALS SHOWN ARE DIFFERENTIAL. FOR EXAMPLE, PCLKO = (PCLKO+) - (PCLKO-).
*PDI 15 = D15; PDI14 = D14; ...PDI0 = D0.
THIS FIGURE IS NOT INTENDED TO SHOW A SPECIFIC TIMING RELATIONSHIP BETWEEN PARALLEL
INPUT DATA AND SERIAL OUTPUT DATA.
Figure 2. Timing Diagram
Low-Voltage Differential-Signal
Inputs and Outputs
The MAX3890 has LVDS inputs and outputs for inter-
facing with high-speed digital circuitry. The LVDS
standard is based on the IEEE 1596.3 LVDS specifi-
cation. This technology uses 250mV to 400mV differ-
ential low-voltage swings to achieve fast transition
times, minimized power dissipation, and noise immu-
nity.
For proper operation, the parallel clock LVDS outputs
(PCLKO+, PCLKO-) require 100Ω differential DC termi-
nation between the inverting and noninverting outputs.
Do not terminate these outputs to ground.
The parallel data and parallel clock LVDS inputs
(PDI_+, PDI_-, PCLKI+, PCLKI-, RCLK+, RCLK-) are
internally terminated with 100Ω differential input resis-
tance, and therefore do not require external termina-
tion.
PECL Outputs
The serial-data PECL outputs (SDO+, SDO-, SCLKO+,
SCLKO-) require 50Ω DC termination to (VCC - 2V) (see
the Alternative PECL-Output Termination section).
Current-Mode Logic Outputs
The system loopback outputs (SLBO+, SLBO-) of the
MAX3890 are designed using CML. The configuration
of the MAX3890 current-mode logic (CML) output cir-
cuit includes internal 50Ω back termination to VCC
(Figure 3). These outputs are intended to drive a 50Ω
transmission line terminated with a matched load
impedance.
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