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CD4514BC

4-Bit Latched/4-to-16 Line Decoders

Fairchild Semiconductor 

October 1987

Revised August 2000

CD4514BC• CD4515BC

4-Bit Latched/4-to-16 Line Decoders

General Description

The CD4514BC and CD4515BC are 4-to-16 line decoders

with latched inputs implemented with complementary MOS

(CMOS) circuits constructed with N- and P-channel

enhancement mode transistors. These circuits are prima-

rily used in decoding applications where low power dissipa-

tion and/or high noise immunity is required.

The CD4514BC (output active high option) presents a logi-

cal “1” at the selected output, whereas the CD4515BC pre-

sents a logical “0” at the selected output. The input latches

are R–S type flip-flops, which hold the last input data pre-

sented prior to the strobe transition from “1” to “0”. This

input data is decoded and the corresponding output is acti-

vated. An output inhibit line is also available.

Features

s Wide supply voltage range: 3.0V to 15V

s High noise immunity: 0.45 VDD (typ.)

s Low power TTL: fan out of 2

compatibility: driving 74L

s Low quiescent power dissipation:

0.025 µW/package @ 5.0 VDC

s Single supply operation

s Input impedance = 1012Ω typically

s Plug-in replacement for MC14514, MC14515

Ordering Code:

Order Number Package Number

Package Diagram

CD4514BCWM

M24B

24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

CD4514BCN

N24A

24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-011, 0.600 Wide

CD4515BCWM

M24B

24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

CD4515BCN

N24A

24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-011, 0.600 Wide

Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Connection Diagram

Top View

© 2000 Fairchild Semiconductor Corporation DS005994

www.fairchildsemi.com

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