CAT1021, CAT1022, CAT1023
Table 9. RESET CIRCUIT AC CHARACTERISTICS
Symbol
Parameter
tPURST
tRDP
tGLITCH
MR Glitch
Power−Up Reset Timeout
VTH to RESET output Delay
VCC Glitch Reject Pulse Width
Manual Reset Glitch Immunity
tMRW
tMRD
tWD
MR Pulse Width
MR Input to RESET Output Delay
Watchdog Timeout
Test Conditions
Note 2
Note 3
Notes 4 and 5
Note 1
Note 1
Note 1
Note 1
Min
Typ
Max Units
130
200
270
ms
5
ms
30
ns
100
ns
5
ms
1
ms
1.0
1.6
2.1
sec
Table 10. POWER−UP TIMING (Notes 5 and 6)
Symbol
Parameter
tPUR
tPUW
Power−Up to Read Operation
Power−Up to Write Operation
Test Conditions
Min
Typ
Max Units
270
ms
270
ms
Table 11. AC TEST CONDITIONS
Parameter
Input Pulse Voltages
Input Rise and Fall Times
Input Reference Voltages
Output Reference Voltages
Output Load
Test Conditions
0.2 x VCC to 0.8 x VCC
10 ns
0.3 x VCC , 0.7 x VCC
0.5 x VCC
Current Source: IOL = 3 mA; CL = 100 pF
Table 12. RELIABILITY CHARACTERISTICS
Symbol
Parameter
Reference Test Method
Min
Max
Units
NEND (Note 5) Endurance
MIL−STD−883, Test Method 1033
1,000,000
Cycles/Byte
TDR (Note 5) Data Retention
MIL−STD−883, Test Method 1008
100
Years
VZAP (Note 5) ESD Susceptibility
MIL−STD−883, Test Method 3015
2000
Volts
ILTH (Notes 5 & 7) Latch−Up
JEDEC Standard 17
100
mA
1. Test Conditions according to “AC Test Conditions” table.
2. Power−up, Input Reference Voltage VCC = VTH, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table
3. Power−Down, Input Reference Voltage VCC = VTH, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table
4. VCC Glitch Reference Voltage = VTHmin; Based on characterization data
5. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
6. tPUR and tPUW are the delays required from the time VCC is stable until the specified memory operation can be initiated.
7. Latch−up protection is provided for stresses up to 100 mA on input and output pins from −1 V to VCC + 1 V.
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