C8051F121-GQ 데이터 시트보기 (PDF) - Silicon Laboratories

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C8051F121-GQ

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F120/1/2/3/4/5/6/7

C8051F130/1/2/3

VDD

VDD

VDD

DGND

DGND

DGND

AV+

AV+

AGND

AGND

TCK

TMS

TDI

TDO

RST

MONEN

XTAL1

XTAL2

VREF

VREFD

DAC1

DAC0

VREF0

AIN0.0

AIN0.1

AIN0.2

AIN0.3

AIN0.4

AIN0.5

AIN0.6

AIN0.7

CP0+

CP0-

CP1+

CP1-

Digital Power

Analog Power

8

JTAG Boundary Scan

Logic

Debug HW

VDD

Monitor

WDT

0

5 Reset

1

External Oscillator

Circuit

PLL

Circuitry

Calibrated Internal

Oscillator

VREF

DAC1

(12-Bit)

System

C

Clock

o

r

e

DAC0

(12-Bit)

SFR Bus

256 byte

RAM

8 kB

XRAM

External Data

Memory Bus

128 kB

FLASH

64x4 byte

cache

A

M

Prog

U

Gain

X

CP0

TEMP

SENSOR

CP1

ADC

100 ksps

(12-Bit)

Port I/O

Config.

UART0

UART1

SMBus

SPI Bus

PCA

Timers 0,

1, 2, 4

Timer 3/

RTC

P0, P1,

P2, P3

Latches

Crossbar

Config.

P0

Drv

C

R

P1

O

Drv

S

S

B

P2

Drv

A

R

P3

Drv

ADC

500 ksps

(8-Bit)

A

Prog

M 8:1

Gain

U

X

Bus Control

C P4 Latch

T

L

Address Bus

P5 Latch

A

d

d P6 Latch

r

P4

DRV

P5

DRV

P6

DRV

Data Bus

D P7 Latch

a

t

a

P7

DRV

Figure 1.1. C8051F120/124 Block Diagram

P0.0

P0.7

P1.0/AIN2.0

P1.7/AIN2.7

P2.0

P2.7

P3.0

P3.7

VREF2

P4.0

P4.4

P4.5/ALE

P4.6/RD

P4.7/WR

P5.0/A8

P5.7/A15

P6.0/A0

P6.7/A7

P7.0/D0

P7.7/D7

Rev. 1.4

21

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