WED9LAPC2C16V8BC 데이터 시트보기 (PDF) - White Electronic Designs => Micro Semi
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WED9LAPC2C16V8BC Datasheet PDF : 24 Pages
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White Electronic Designs WED9LAPC2C16V8BC
MODE REGISTER FIELD TABLE TO PROGRAM MODES
REGISTER PROGRAMMED WITH MRS
Address BA0 A9/AP A8
A10 A7 A6 A5 A4 A3 A2 A1 A2
Function RFU RFU W.B.L.
TM
CAS Latency
BT
Burst Length
Test Mode
A10 A7
Type
A6
0 0 Mode Register Set 0
01
Reserved
0
10
Reserved
0
11
Reserved
0
Write Burst Length
1
A9
Length
1
0
Burst
1
1
Single Bit
1
Full Page Length: x32 (256)
CAS Latency
Burst Type
A5 A4 Latency A3 Type A2
0 0 Reserved 0 Sequential 0
0 1 Reserved 1 Interleave 0
10
2
0
11
3
0
0 0 Reserved
1
0 1 Reserved
1
1 0 Reserved
1
1 1 Reserved
1
Burst Length
A1 A0 BT = 0 BT = 1
00
1
1
01
2
2
10
4
4
11
8
8
0 0 Reserved Reserved
0 1 Reserved Reserved
1 0 Reserved Reserved
1 1 Full Page Reserved
POWER UP SEQUENCE
SDRAMs must be powered up and initialized in a
predefined manner to prevent undefined operations.
1.
Apply power and start clock. Must maintain
CKE= “H”,DQM = “H” and the other pins are
NOP condition at the inputs.
2.
Maintain stable power, stable clock and NOP
input condition for a minimum of 200µs.
3.
Issue precharge commandes for all banks of
the devices.
4.
Issue 2 or more auto-refresh commands.
5.
Issue a mode register set command to initialize
the mode register.
cf.)
Sequence of 4 & 5 is regardless of the order.
The device is now ready for normal operation.
Note:
1. If A8 is high during MRS cycle, “Burst Read Single Bit Write” function will be
enabled.
2. RFU (Reserved for future use) shuld stay “0” during MRS cycle.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July, 2000
Rev. 0
23
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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