WED9LAPC2C16V8BC 데이터 시트보기 (PDF) - White Electronic Designs => Micro Semi

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WED9LAPC2C16V8BC

512K x 32 SSRAM / 1M x 64 SDRAM

White Electronic Designs => Micro Semi 

White Electronic Designs WED9LAPC2C16V8BC

FIG. 14 SDRAM BURST READ SINGLE BIT WRITE CYCLE @ BURST LENGTH = 2

0

1

2

3

4

5

6

7

8

9

10

11 12

13

14

15

16 17

18

19

GCK

VCRAS#

VCCAS#

Note 2

VCADDR

RAa

CAa RBb CAb

RAc

CBc

CAd

VCBS

VCADDR9/AP

RAa

CL = 2

VCDATA

CL = 3

RBb

DAa0

DAa0

RAc

QAb0 QAb1

QAb0 QAb1

DBc0

DBc0

QAd0 QAd1

QAd0 QAd1

VCWE#

VCDQM#

Row Active

(A-Bank)

Row Active

(B-Bank)

Write

(A-Bank)

Read with

Auto Precharge

(A-Bank)

Row Active

(A-Bank)

Write with

Auto Precharge

(B-Bank)

Read

(A-Bank)

Precharge

(Both Banks)

DON’T CARE

Notes:

1. BRSW modes enabled by setting A9 “High” at MRS (Mode Register Set).

At the BRSW Mode, the burst length at Write is fixed to “1” regardless of programmed burst length.

2. When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated. Auto precharge is executed at the burst-end cycle, so in

the case of BRSW write command, the next cycle starts the precharge.

White Electronic Designs Corp. reserves the right to change products or specifications without notice.

July, 2000

Rev. 0

21

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

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