5962-9154507MXX 데이터 시트보기 (PDF) - Atmel Corporation
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5962-9154507MXX Datasheet PDF : 21 Pages
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ATV2500B(Q)(L)
Level Forced on
Odd I/O Pin
during
PRELOAD Cycle
VIH/VIL
VIH/VIL
VIH/VIL
VIH/VIL
Q Select Pin
State
Low
High
Low
High
Even/Odd Select
Low
Low
High
High
Even Q1 State
after Cycle
High/Low
X
X
X
Power-up Reset
The registers in the ATV2500Bs are designed to reset dur- .
ing power-up. At a point delayed slightly from VCC crossing
VRST, all registers will be reset to the low state. The output
state will depend on the polarity of the output buffer.
This feature is critical for state as nature of reset and the
uncertainty of how VCC actually rises in the system, the fol-
lowing conditions are required:
1. The VCC rise must be monotonic,
2. After reset occurs, all input and feedback setup
times must be met before driving the clock pin or
terms high, and
3. The clock pin, and any signals from which clock
terms are derived, must remain stable during tPR.
Parameter
tPR
VRST
Description
Power-up Reset Time
Power-up Reset Voltage
Even Q2 State
after Cycle
X
High/Low
X
X
Typ
600
3.8
Odd Q1 State
after Cycle
X
X
High/Low
X
Max
1000
4.5
Odd Q2 State
after Cycle
X
X
X
High/Low
Units
ns
V
11
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