TS80C31X2-MIC(2008) 데이터 시트보기 (PDF) - Atmel Corporation
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TS80C31X2-MIC Datasheet PDF : 42 Pages
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AT/TS80C31X2
Mnemonic
VSS
Vss1
VCC
P0.0-P0.7
P1.0-P1.7
P2.0-P2.7
P3.0-P3.7
Reset
ALE
PSEN
Pin Number
DIL
LCC
VQFP 1.4
20
22
16
1
39
40
44
38
39-
32
43-36
37-30
1-8
2-9
40-44
1-3
21-
28
24-31
18-25
10-
17
11,
13-19
5,
7-13
10
11
5
11
13
7
12
14
8
13
15
9
14
16
10
15
17
11
16
18
12
17
19
13
9
10
4
30
33
27
29
32
26
Type
I
I
I
I/O
I/O
I/O
I/O
I
O
I
I
I
I
O
O
I
O (I)
O
Name And Function
Ground: 0V reference
Optional Ground: Contact the Sales Office for ground connection.
Power Supply: This is the power supply voltage for normal, idle and power-down
operation
Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written
to them float and can be used as high impedance inputs. Port 0 pins must be
polarized to Vcc or Vss in order to prevent any parasitic current consumption. Port 0
is also the multiplexed low-order address and data bus during access to external
program and data memory. In this application, it uses strong internal pull-up when
emitting 1s.
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that
have 1s written to them are pulled high by the internal pull-ups and can be used as
inputs. As inputs, Port 1 pins that are externally pulled low will source current
because of the internal pull-ups.
Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that
have 1s written to them are pulled high by the internal pull-ups and can be used as
inputs. As inputs, Port 2 pins that are externally pulled low will source current
because of the internal pull-ups. Port 2 emits the high-order address byte during
fetches from external program memory and during accesses to external data
memory that use 16-bit addresses (MOVX @DPTR).In this application, it uses
strong internal pull-ups emitting 1s. During accesses to external data memory that
use 8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 SFR.
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that
have 1s written to them are pulled high by the internal pull-ups and can be used as
inputs. As inputs, Port 3 pins that are externally pulled low will source current
because of the internal pull-ups. Port 3 also serves the special features of the
80C51 family, as listed below.
RXD (P3.0): Serial input port
TXD (P3.1): Serial output port
INT0 (P3.2): External interrupt 0
INT1 (P3.3): External interrupt 1
T0 (P3.4): Timer 0 external input
T1 (P3.5): Timer 1 external input
WR (P3.6): External data memory write strobe
RD (P3.7): External data memory read strobe
Reset: A high on this pin for two machine cycles while the oscillator is running,
resets the device. An internal diffused resistor to VSS permits a power-on reset using
only an external capacitor to VCC.
Address Latch Enable: Output pulse for latching the low byte of the address during
an access to external memory. In normal operation, ALE is emitted at a constant
rate of 1/6 (1/3 in X2 mode) the oscillator frequency, and can be used for external
timing or clocking. Note that one ALE pulse is skipped during each access to
external data memory.
Program Store ENable: The read strobe to external program memory. When
executing code from the external program memory, PSEN is activated twice each
machine cycle, except that two PSEN activations are skipped during each access to
external data memory. PSEN is not activated during fetches from internal program
memory.
5
4428E–8051–02/08
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