
AC Test Conditions (Continued)
FIGURE 1. Synchronous Data Timing Diagram
VIH
CS
VIL
tCSS
VIH
SCK
VIL
VIH
,, SI
VIL
VOH
SO
, VOL
tCLH
tCLL
tDIS
tPD
tDIN
tDH
tCSH
tCSN
tDF
FIGURE 2. HOLD Timing
SCK
tHDS
HOLD
SO
tHDN
tHZ
tHDS
tHDN
tLZ
FIGURE 3. SPI Serial Interface
MASTER MCU
DATA OUT (MOSI)
DATA IN (MISO)
SERIAL CLOCK (CLK)
SPI
SS0
CHIP
SS1
SELECTION SS2
SS3
5
NM25C020 Rev. D.1
NM25C020
SI
SO
SCK
CS
SI
SO
SCK
CS
SI
SO
SCK
CS
SI
SO
SCK
CS
DS012400-3
DS012400-6
DS012400-4
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