PIC14000T-04I/SP 데이터 시트보기 (PDF) - Microchip Technology

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PIC14000T-04I/SP

28-Pin Programmable Mixed Signal Controller

Microchip Technology 

PIC14000

4.2.2.3 INTCON REGISTER

The INTCON Register is a readable and writable

register which contains the various enable and flag bits

for the Timer0 overflow and peripheral interrupts.

Figure 4-5 shows the bits for the INTCON register.

Note:

The T0IF will be set by the specified

condition even if the corresponding Inter-

rupt Enable Bit is cleared (interrupt

disabled) or the GIE bit is cleared (all

interrupts disabled). Before enabling

interrupt, clear the interrupt flag, to ensure

that the program does not immediately

branch to the peripheral interrupt service

routine

FIGURE 4-5: INTCON REGISTER

R/W R/W R/W

GIE PEIE T0IE

bit7

R/W R/W R/W R/W

r

r T0IF r

R/W

r

bit0

Register:

INTCON W:

Address: 0Bh or 8Bh R:

POR value: 0000 000xb U:

Writable

Readable

Unimplemented,

read as '0'

Reserved. This bit should be programmed as ‘0’. Use of this bit

as a general purpose read/write bit is not recommended, since

this may affect upward compatibility with future products.

Reserved. This bit should be programmed as ‘0’. Use of this bit

as a general purpose read/write bit is not recommended, since

this may affect upward compatibility with future products.

T0IF: TMR0 overflow interrupt flag

1 = The TMR0 has overflowed

Must be cleared by software

0 = TMR0 did not overflow

Reserved. This bit should be programmed as ‘0’. Use of this bit

as a general purpose read/write bit is not recommended, since

this may affect upward compatibility with future products.

Reserved. This bit should be programmed as ‘0’. Use of this bit

as a general purpose read/write bit is not recommended, since

this may affect upward compatibility with future products.

T0IE: TMR0 interrupt enable bit

1 = Enables T0IF interrupt

0 = Disables T0IF interrupt

PEIE: Peripheral interrupt enable bit

1 = Enables all un-masked peripheral interrupts

0 = Disables all peripheral interrupts

GIE: Global interrupt enable

1 = Enables all un-masked interrupts

0 = Disables all interrupts

© 1996 Microchip Technology Inc.

Preliminary

DS40122B-page 19

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