QuASI Interface
PRELIMINARY
1
SCLK
QRST/STRB
QTX_EN
QTX_DATA
QRX_DATA
QRX_VALID
QRX_CRS
QCLSN
23
45
23
9
67
9B
Not Defined Channel 0 Channel 1 Channel 2 Channel 3 Channel 0 Channel 1
8
Not defined
Channel 3 Channel 0 Channel 1 Channel 2 Channel 3
Figure 2. QuASI Interface Timing Diagram
21173B-6
No.
Symbol
Parameter Description
Min
Max
Unit
1
tMSI1
SCLK Period (40 MHz, 100 ppm).
Not Tested.
24.9975 25.0025 ns
2
tMSI2
QRST/STRB hold time after rising edgeof SLCK.
3
ns
3
tMSI3
QRST/STRB setup time to rising edge of SCLK.
5
ns
4
tMSI4
SCLK high time.
10
ns
5
tMSI5
SCLK low time.
10
ns
6
tMSI6
QTX_EN and QTX_DATA setup time to rising edge of SCLK.
3
ns
7
tMSI7
QTX_EN and QTX_DATA hold time from rising edge of SCLK.
5
ns
8
tMSI8
QRX_DATA, QRX_VALID, QCLSN, QRX_CRS delay until valid
from rising edge of SCLK.
4
17.5
ns
Reset Pulse Width of QRST/STRB.
9
tMSI9
Parameter tested functionally.
1
µs
9B
tMSI9B
Strobe Pulse Width of QRST/STRB.
9
25
ns
32
Am79C989