PRELIMINARY
SWITCHING CHARACTERISTICS (continued)
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
Twisted Pair Port Timing
tTXTD CLK Rising Edge to TXD± Transition Delay
–
50
ns
tTETD Transmit End of Transmission
250
375
ns
tPWKRD RXD Pulse Width Maintain/Turn-off
|VIN|>|VTHS| (Note 6)
136
200
ns
Threshold
tPERLP Idle Signal Period
tPWLP Idle Link Test Pulse Width
Control Port Timing
8
24
ms
75
120
ns
tSCLK
tSCLKH
tSCLKL
tSCLKR
tSCLKF
tSISET
tSIHLD
tSODLY
SCLK Clock Period
SCLK Clock HIGH
SCLK Clock LOW
SCLK Clock Rise Time
SCLK Clock Fall Time
SI Input Setup Time to SCLK Rising Edge
SI Input Hold Time from SCLK Rising Edge
SO Output Delay from SCLK Rising Edge CL = 100 pF
100
–
ns
30
–
ns
30
–
ns
–
10
ns
–
10
ns
10
–
ns
10
–
ns
–
40
ns
Notes:
1. Parameter not tested.
2. DI pulses narrower than tPWODI (min) will be rejected; pulses wider than tPWODI (max) will turn internal DI carrier sense on.
3. DI pulses narrower than tPWKDI (min) will maintain internal DI carrier on; pulses wider than tPWKDI (max) will turn internal DI
carrier sense off.
4. CI pulses narrower than tPWOCI (min) will be rejected; pulses wider than tPWOCI (max) will turn internal CI carrier sense on.
5. CI pulses narrower than tPWKCI (min) will maintain internal CI carrier on; pulses wider than tPWKCI (max) will turn internal CI
carrier sense off.
6. RXD pulses narrower than tPWKRD (min) will maintain internal RXD carrier sense on; a pulse wider than tPWKRD (max) will turn
RXD carrier sense off.
Am79C984A
35