AM53C94KC 데이터 시트보기 (PDF) - Advanced Micro Devices

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AM53C94KC

High Performance SCSI Controller

Advanced Micro Devices 

AMD

PRELIMINARY

SELC

Select Control

(Output, Active Low, Open Drain)

This is a SCSI output with 48 mA drive. When the device

is configured in the Single Ended SCSI Mode (DFMODE

inactive) this pin is defined as a SEL output for the SCSI

bus. When the device is configured in the Differential

SCSI Mode (DFMODE active) this pin is defined as the

direction control for the external differential transceiver.

In this mode, a signal high state corresponds to an out-

put to the SCSI bus and a low state corresponds to an

input from the SCSI bus.

REQC

Request Control

(Output, Active Low, Open Drain)

This is a SCSI output with 48 mA drive. This signal is ac-

tivated only in the target mode.

ACKC

Acknowledge Control

(Output, Active Low, Open Drain)

This is a SCSI output with 48 mA drive. This signal is ac-

tivated only in the initiator mode.

RSTC

Reset Control

(Output, Active Low, Open Drain)

This is a SCSI output with 48 mA drive. The Reset SCSI

command will cause the device to drive RSTC active for

25 ms–40 ms, which will depend on the CLK frequency

and the conversion factor. When the device is config-

ured in the Single Ended SCSI Mode (DFMODE inac-

tive) this pin is defined as a RST output for the SCSI bus.

When the device is configured in the Differential SCSI

Mode (DFMODE active) this pin is defined as the direc-

tion control for the external differential transceiver. In

this mode, a signal high state corresponds to an output

to the SCSI bus and a low state corresponds to an input

from the SCSI bus.

ISEL

Initiator Select

(Output, Active High)

This signal is available on the Am53C96 only. This sig-

nal is active whenever the device is in the initiator mode.

In the differential mode this signal is used to enable the

initiator signals ACKC and ATN and the device also

drives these signals.

TSEL

Target Select

(Output, Active High)

This signal is available on the Am53C96 only. This sig-

nal is active whenever the device is in the target mode.

In the differential mode this signal is used to enable the

target signals REQC, MSG, C/D and I/O and the device

also drives these signals.

FUNCTIONAL DESCRIPTION

Register Map

Address

(Hex.) Operation Register

Address

(Hex.) Operation Register

00

Read Current Transfer Count

Register LSB

00

Write Start Transfer Count Register

LSB

01

Read Current Transfer Count

Register MSB

01

Write Start Transfer Count Register

MSB

02 Read/Write FIFO Register

03 Read/Write Command Register

04

Read Status Register

04

Write SCSI Destination ID Register

05

Read Interrupt Status Register

05

Write SCSI Timeout Register

06

Read Internal State Register

06

Write Synchronous Transfer Period

Register

07

Read Current FIFO/Internal State

Register

07

Write Synchronous Offset Register

08 Read/Write Control Register 1

09

Write Clock Factor Register

0A

Write Forced Test Mode Register

0B Read/Write Control Register 2

0C Read/Write Control Register 3

0F

Write Data Alignment Register

Note:

Not all registers in this device are both readable and writable. Some read only registers share the same address with write only

registers. The registers can be accessed by asserting the CS signal and then asserting either RD or WR signal depending on the

operation to be performed. Only the FIFO Register can be accessed by asserting either CS or DACK in conjunction with RD and

WR signals or DMARD and DMAWR signals. The register address inputs are ignored when DACK is used but must be valid

when CS is used.

16

Am53C94/Am53C96

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