AKD4382 데이터 시트보기 (PDF) - Asahi Kasei Microdevices
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AKD4382 Datasheet PDF : 21 Pages
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ASAHI KASEI
[AK4382]
SWITCHING CHARACTERISTICS
(Ta=25°C; VDD=4.5 ~ 5.5V; CL=20pF)
Parameter
Symbol
min
typ
Master Clock Frequency
Duty Cycle
fCLK
dCLK
2.048
40
11.2896
LRCK Frequency
Normal Speed Mode
fsn
8
Double Speed Mode
fsd
60
Quad Speed Mode
fsq
120
Duty Cycle
Duty
45
Audio Interface Timing
BICK Period
Normal Speed Mode
Double/Quad Speed Mode
BICK Pulse Width Low
Pulse Width High
BICK rising to LRCK Edge (Note 12)
LRCK Edge to BICK rising (Note 12)
SDTI Hold Time
SDTI Setup Time
tBCK
tBCK
tBCKL
tBCKH
tBLR
tLRB
tSDH
tSDS
1/128fs
1/64fs
30
30
20
20
20
20
Control Interface Timing
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “¯” to CCLK “”
CCLK “” to CSN “”
Rise Time of CSN
Fall Time of CSN
Rise Time of CCLK
Fall Time of CCLK
tCCK
200
tCCKL
80
tCCKH
80
tCDS
40
tCDH
40
tCSW
150
tCSS
50
tCSH
50
tR1
tF1
tR2
tF2
Reset Timing
PDN Pulse Width
(Note 13) tPD
100
Notes: 12. BICK rising edge must not occur at the same time as LRCK edge.
13. The AK4382 can be reset by bringing PDN= “L”.
max
36.864
60
48
96
192
55
20
20
20
20
Units
MHz
%
kHz
kHz
kHz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MS0034-E-00
-6-
2000/7
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