
ADV7314
CLKIN_B
CONTROL
INPUTS
P_HSYNC,
P_VSYNC,
P_BLANK
t9
t10
Y9–Y0
Cb0
Y0
t12
t11
Cr0
Y1
t12
t11
Crxxx Yxxx
PS INPUT
CLKIN_A
t9 t10
t12
CONTROL
INPUTS
S_HSYNC,
S_VSYNC,
S_BLANK
S9–S0
Cb0
Y0
Cr0
Y1
Cb1
Y2
t11
Figure 10. PS (10-Bit) and SD (10-Bit) Simultaneous Input Mode [Input Mode 100]
SD INPUT
CLKIN_A
t9 t10
t12
CONTROL
INPUTS
S_HSYNC,
S_VSYNC,
S_BLANK
IN SLAVE MODE
S9–S0/Y9–Y0*
Cb0
Cr0
Cb2
Cr2
Cb4
Cr4
t11
CONTROL
OUTPUTS
t13
t14
*SELECTED BY ADDRESS 0x01 BIT 7
Figure 11. 10-/8-Bit SD Only Pixel Input Mode [Input Mode 000]
IN MASTER/SLAVE MODE
REV. 0
–11–