ADSP-21991 데이터 시트보기 (PDF) - Analog Devices
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ADSP-21991 Datasheet PDF : 44 Pages
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ADSP-21991
SPECIFICATIONS
Specifications subject to change without notice.
RECOMMENDED OPERATING CONDITIONS—ADSP-21991BBC
Parameter
Min
Typ
Max
Unit
VDDINT
VDDEXT
AVDD
CCLK
HCLK1, 2
CLKIN3
TJUNC4
TAMB
Internal (Core) Supply Voltage
External (I/O) Supply Voltage
Analog Supply Voltage
DSP Instruction Rate, Core Clock
Peripheral Clock Rate
Input Clock Frequency
Silicon Junction Temperature
Ambient Operating Temperature
2.375
3.135
2.375
0
0
0
–40
2.5
2.625
3.3
3.465
2.5
2.625
150
75
150
+140
+85
V
V
V
MHz
MHz
MHz
ºC
ºC
1 The HCLK frequency may be made to appear at the dedicated CLKOUT pin of the device. For low power operation, however, the CLKOUT pin can be
disabled.
2 The peripherals operate at the HCLK rate, which may be selected to be equal to CCLK or CCLK،2, up to a maximum of a 75 MHz HCLK for the
ADSP-21991BBC.
3 In order to attain the correct CCLK and HCLK values, the input clock frequency or crystal frequency depends on the internal operation of the clock
generation PLL circuit and the associated frequency ratio.
4 The maximum junction temperature is limited to 140°C in order to meet all of the electrical specifications. It is ultimately the responsibility of the user to
ensure that the power dissipation of the ADSP-21991 (including all dc and ac loads) is such that the maximum junction temperature limit of 140°C is not
exceeded.
RECOMMENDED OPERATING CONDITIONS—ADSP-21991BST
Parameter
Min
Typ
Max
Unit
VDDINT
VDDEXT
AVDD
CCLK
HCLK1, 2
CLKIN3
TJUNC4
TAMB
Internal (Core) Supply Voltage
External (I/O) Supply Voltage
Analog Supply Voltage
DSP Instruction Rate, Core Clock
Peripheral Clock Rate
Input Clock Frequency
Silicon Junction Temperature
Ambient Operating Temperature
2.375
3.135
2.375
0
0
0
–40
2.5
2.625
3.3
3.465
2.5
2.625
160
80
160
+140
+85
V
V
V
MHz
MHz
MHz
ºC
ºC
1 The HCLK frequency may be made to appear at the dedicated CLKOUT pin of the device. For low power operation, however, the CLKOUT pin can be
disabled.
2 The peripherals operate at the HCLK rate, which may be selected to be equal to CCLK or CCLK،2, up to a maximum of an 80 MHz HCLK for the
ADSP-21991BST.
3 In order to attain the correct CCLK and HCLK values, the input clock frequency or crystal frequency depends on the internal operation of the clock
generation PLL circuit and the associated frequency ratio.
4 The maximum junction temperature is limited to 140°C in order to meet all of the electrical specifications. It is ultimately the responsibility of the user to
ensure that the power dissipation of the ADSP-21991 (including all dc and ac loads) is such that the maximum junction temperature limit of 140°C is not
exceeded.
REV. 0
–17–
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