ADSP-21469KBZ-ENG2 데이터 시트보기 (PDF) - Analog Devices
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ADSP-21469KBZ-ENG2 Datasheet PDF : 56 Pages
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ADSP-21469/ADSP-21469W
Preliminary Technical Data
Clock Input
Table 14. Clock Input
450 MHz
Parameter
Min
Timing Requirements
tCK
CLKIN Period
tCKL
CLKIN Width Low
tCKH
CLKIN Width High
TBD1
TBD1
TBD1
tCKRF
tCCLK3
CLKIN Rise/Fall (0.4 V to 2.0 V)
CCLK Period
2.221
1 Applies only for CLKCFG1–0 = 00 and default values for PLL control bits in PMCTL.
2 Applies only for CLKCFG1–0 = 01 and default values for PLL control bits in PMCTL.
3 Any changes to PLL control bits in the PMCTL register must meet core clock timing specification tCCLK.
Max
TBD2
TBD2
TBD2
TBD
TBD
Unit
ns
ns
ns
ns
ns
CLKIN
tCKH
tCK
tCKL
Figure 5. Clock Input
Clock Signals
The ADSP-21469 can use an external clock or a crystal. See the
CLKIN pin description in Table 6. The programmer can config-
ure the ADSP-21469 to use its internal clock generator by
connecting the necessary components to CLKIN and XTAL.
Figure 6 shows the component connections used for a crystal
operating in fundamental mode. Note that the clock rate is
achieved using a 28.125 MHz crystal and a PLL multiplier ratio
16:1 (CCLK:CLKIN achieves a clock speed of 450 MHz). To
achieve the full core clock rate, programs need to configure the
multiplier bits in the PMCTL register.
CLKIN
C1
22pF
ADSP-21469
R1
1M⍀*
Y1
28.125 MHz
XTAL
R2
47⍀*
C2
22pF
R2 SHOULD BE CHOSEN TO LIMIT CRYSTAL
DRIVE POWER. REFER TO CRYSTAL
MANUFACTURER’S SPECIFICATIONS
*TYPICAL VALUES
Figure 6. 450 MHz Operation (Fundamental Mode Crystal)
Rev. PrB | Page 22 of 56 | November 2008
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