ADSP-21469KBZ-ENG2 데이터 시트보기 (PDF) - Analog Devices

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ADSP-21469KBZ-ENG2

SHARC Processor

Analog Devices 

ADSP-21469/ADSP-21469W

Table 12. Clock Periods

Timing

Requirements

Description1

tCK

CLKIN Clock Period

tCCLK

(Processor) Core Clock Period

tLCLK

(Link Port) Core Clock Period

tPCLK

(Peripheral) Clock Period = 2 × tCCLK

tSCLK

Serial Port Clock Period = (tPCLK) × SR

tDDR2_CLK

DDR2 DRAM Clock Period = (tCCLK) × SDR

tSPICLK

SPI Clock Period = (tPCLLK) × SPIR

1 where:

SR = serial port-to-core clock ratio (wide range, determined by SPORT CLKDIV

bits in DIVx register)

SPIR = SPI-to-Core Clock Ratio (wide range, determined by SPIBAUD register

setting)

SDR=DDR2 DRAM-to-Core Clock Ratio (Values determined by bits 20-18 of

the PMCTL register)

Preliminary Technical Data

Use the exact timing information given. Do not attempt to

derive parameters from the addition or subtraction of others.

While addition or subtraction would yield meaningful results

for an individual device, the values given in this data sheet

reflect statistical variations and worst cases. Consequently, it is

not meaningful to add parameters to derive longer times. See

Figure 41 on Page 50 under Test Conditions for voltage refer-

ence levels.

Switching Characteristics specify how the processor changes its

signals. Circuitry external to the processor must be designed for

compatibility with these signal characteristics. Switching char-

acteristics describe what the processor will do in a given

circumstance. Use switching characteristics to ensure that any

timing requirement of a device connected to the processor (such

as memory) is satisfied.

Timing Requirements apply to signals that are controlled by cir-

cuitry external to the processor, such as the data input for a read

operation. Timing requirements guarantee that the processor

operates correctly with other devices.

Rev. PrB | Page 20 of 56 | November 2008

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