ADSP-21266SKSTZ-1C 데이터 시트보기 (PDF) - Analog Devices
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ADSP-21266SKSTZ-1C Datasheet PDF : 44 Pages
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SPI Interface Protocol—Slave
See Table 31 and Figure 26.
Table 31. SPI Interface Protocol—Slave
Parameter
Timing Requirements
tSPICLKS
tSPICHS
tSPICLS
tSDSCO
Serial Clock Cycle
Serial Clock High Period
Serial Clock Low Period
SPIDS Assertion to First SPICLK Edge
CPHASE = 0
CPHASE = 1
tHDS
tSSPIDS
tHSPIDS
tSDPPW
Last SPICLK Edge to SPIDS Not Asserted CPHASE = 0
Data Input Valid to SPICLK Edge (Data Input Setup Time)
SPICLK Last Sampling Edge to Data Input Not Valid
SPIDS Deassertion Pulse Width (CPHASE = 0)
Switching Characteristics
tDSOE
tDSDHI
tDDSPIDS
tHDSPIDS
tDSOV
SPIDS Assertion to Data Out Active
SPIDS Deassertion to Data High Impedance
SPICLK Edge to Data Out Valid (Data Out Delay Time)
SPICLK Edge to Data Out Not Valid (Data Out Hold Time)
SPIDS Assertion to Data Out Valid (CPHASE = 0)
ADSP-21266
Min
4 × tCCLK
2 × tCCLK – 2
2 × tCCLK – 2
2 × tCCLK + 1
2 × tCCLK + 1
2 × tCCLK
2
2
2 × tCCLK
0
0
2 × tCCLK – 2
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
ns
5
ns
7.5
ns
ns
5 × tCCLK + 2 ns
SPIDS
(INPUT)
SPICLK
(CP = 0)
(INPUT)
tSDSCO
SPICLK
(CP = 1)
(INPUT)
tDSOE
tS P IC H S
tSPICLS
tDDSPIDS
tSPICLS
tSPICHS
tSPICLKS
tHDS
tDDSPIDS
MISO
(OUTPUT)
MSB
CPHASE = 1
tSSPIDS
MOSI
(INPUT)
tDSOV
tD S O E
MISO
(OUTPUT)
MSB VALID
MSB
tDDSPIDS
CPHASE = 0
MOSI
(INPUT)
MSB VALID
tSSPIDS
LSB
tHSPIDS
LSB VALID
tHDSPIDS
LSB
tSSPIDS
tHSPIDS
LSB VALID
tSDPPW
tDSDHI
tHDSPIDS
tDSDHI
Figure 26. SPI Interface Protocol—Slave
Rev. B | Page 35 of 44 | May 2005
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