ADSP-21061LKS-160 데이터 시트보기 (PDF) - Analog Devices

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ADSP-21061LKS-160

ADSP-2106x SHARC® DSP Microcomputer Family

Analog Devices 

Pin

TFSx

RFSx

EBOOT

LBOOT

BMS

CLKIN

RESET

TCK

TMS

TDI

TDO

TRST

EMU

ICSA

VDD

GND

NC

Type

I/O

I/O

I

I

I/O/T*

I

I/A

I

I/S

I/S

O

I/A

O

O

P

G

ADSP-21061/ADSP-21061L

Function

Transmit Frame Sync (Serial Ports 0, 1).

Receive Frame Sync (Serial Ports 0, 1).

EPROM Boot Select. When EBOOT is high, the ADSP-21061 is configured for booting from an 8-

bit EPROM. When EBOOT is low, the LBOOT and BMS inputs determine booting mode. See table

below. This signal is a system configuration selection which should be hardwired.

Link Boot—Must be tied to GND.

Boot Memory Select. Output: Used as chip select for boot EPROM devices (when EBOOT = 1,

LBOOT = 0). In a multiprocessor system, BMS is output by the bus master. Input: When low, indi-

cates that no booting will occur and that ADSP-21061 will begin executing instructions from external

memory. See table below. This input is a system configuration selection which should be hardwired.

*Three-statable only in EPROM boot mode (when BMS is an output).

EBOOT

LBOOT

BMS

Booting Mode

1

0

Output

EPROM (Connect BMS to EPROM chip select.)

0

0

1 (Input)

Host Processor

0

0

0 (Input)

No Booting. Processor executes from external memory.

Clock In. External clock input to the ADSP-21061. The instruction cycle rate is equal to CLKIN.

CLKIN may not be halted, changed, or operated below the specified frequency.

Processor Reset. Resets the ADSP-21061 to a known state and begins execution at the program

memory location specified by the hardware reset vector address. This input must be asserted (low) at

power-up.

Test Clock (JTAG). Provides an asynchronous clock for JTAG boundary scan.

Test Mode Select (JTAG). Used to control the test state machine. TMS has a 20 kΩ internal pull-up

resistor.

Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a 20 kΩ internal

pull-up resistor.

Test Data Output (JTAG). Serial scan output of the boundary scan path.

Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after power-

up or held low for proper operation of the ADSP-21061. TRST has a 20 kΩ internal pull-up resistor.

Emulation Status. Must be connected to the ADSP-21061 EZ-ICE target board connector only.

Reserved, leave unconnected.

Power Supply; nominally +3.3 V dc for ADSP-21061L, +5.0 V dc for ADSP-21061.

Power Supply Return.

Do Not Connect. Reserved pins which must be left open and unconnected.

REV. B

–11–

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