ADP3121(2009) 데이터 시트보기 (PDF) - ON Semiconductor

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ADP3121
(Rev.:2009)

Dual Bootstrapped, 12 V MOSFET Driver with Output Disable

ON Semiconductor 

ADP3121

PIN CONNECTIONS

BST

IN

OD

VCC

DRVH

SWN

PGND

DRVL

12V

ADP3121

IN 2

VCC

4

DELAY

LATCH

R1

R2 Q

S

OD 3

CMP

1V

CMP

VCC

6

CONTROL

LOGIC

DELAY

D1

BST

1

CBST1

8

DRVH

SW

7

CBST2

RG

RBST

Q1

TO

INDUCTOR

DRVL

5

Q2

PGND

6

Figure 1. Block Diagram

PIN FUNCTION DESCRIPTION

Pin No.

Pin Name

Description

1

BST

Upper MOSFET Floating Bootstrap Supply. A capacitor connected between the BST and SW pins

holds this bootstrapped voltage for the high−side MOSFET while it is switching.

2

IN

Logic Level PWM Input. This pin has primary control of the drive outputs. In normal operation, pulling

this pin low turns on the low−side driver; pulling it high turns on the high−side driver.

3

OD

Output Disable. When low, this pin disables normal operation, forcing DRVH and DRVL low.

4

VCC

Input Supply. This pin should be bypassed to PGND with an ~1 mF ceramic capacitor.

5

DRVL

Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) MOSFET.

6

PGND

Power Ground. This pin should be closely connected to the source of the lower MOSFET.

7

SW

Switch Node Connection. This pin is connected to the buck switching node, close to the upper

MOSFET source. It is the floating return for the upper MOSFET drive signal. It is also used to monitor

the switched voltage to prevent the lower MOSFET from turning on until the voltage is below ~1 V.

8

DRVH

Buck Drive. Output drive for the upper (buck) MOSFET.

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