ADP3181
SPECIFICATIONS
VCC = 12 V, FBRTN = GND, TA = 0°C to +85°C, unless otherwise noted.1
Table 1.
Parameter
ERROR AMPLIFIER
Output Voltage Range2
Accuracy
Line Regulation
Input Bias Current
FBRTN Current
Output Current
Gain Bandwidth Product
Slew Rate
VID INPUTS
Input Low Voltage
Input High Voltage
Input Current
Symbol Conditions
VCOMP
VFB
ΔVFB
IFB
IFBRTN
IO(ERR)
GBW(ERR)
Relative to nominal DAC output, referenced to
FBRTN, CSSUM = CSCOMP. See Figure 3.
VCC = 10 V to 14 V.
FB forced to VOUT − 3%.
COMP = FB.
CCOMP = 10 pF.
VIL(VID)
VIH(VID)
IVID
CPUID > 4.5 V.
CPUID < 4.0 V.
CPUID > 4.5 V.
CPUID < 4.0 V.
VID(X) = 0 V, CPUID > 4.5 V.
VID(X) = 0 V, CPUID < 4.0 V.
Pull-up Resistance
Internal Pull-Up Voltage
VID Transition Delay Time2
No CPU Detection Turn-Off Delay Time2
CPUID INPUT
Input Low Voltage
Input High Voltage
VR 9 Detection Threshold Voltage
Input Current
Pull-Up Resistance
OSCILLATOR
Frequency Range2
Frequency Variation
Output Voltage
RAMPADJ Output Voltage
RAMPADJ Input Current Range
CURRENT SENSE AMPLIFIER
Offset Voltage
Input Bias Current
Gain Bandwidth Product
Slew Rate
Input Common Mode Range
Positioning Accuracy
Output Voltage Range
Output Current
RVID
VIL(CPUID)
VIH(CPUID)
ICPUID
RCPUID
fOSC
fPHASE
VRT
VRAMPADJ
IRAMPADJ
VOS(CSA)
IBIAS(CSSUM)
GBW(CSA)
ΔVFB
ICSCOMP
CPUID > 4.5 V.
CPUID < 4.0 V.
VID code change to FB change.
VID code change to 11111 to PWM going low.
CPUID = 0 V.
TA = +25°C, RT = 250 kΩ, 4-phase.
TA = +25°C, RT = 115 kΩ, 4-phase.
TA = +25°C, RT = 75 kΩ, 4-phase.
RT = 100 kΩ to GND.
RAMPADJ − FB.
CSSUM − CSREF. See Figure 2.
CCSCOMP = 10 pF.
CSSUM and CSREF.
See Figure 4.
Min Typ Max Unit
0.7
−14.5
3.1 V
+14.5 mV
0.05
%
14 15.5 17 μA
100 140 μA
500
μA
20
MHz
25
V/μs
0.8 V
0.4 V
2.0
V
0.8
V
40 70 μA
20 35 μA
40 60
kΩ
2.25 2.5 2.75 V
1.1 1.25 1.4 V
400
ns
400
ns
0.4 V
0.8
4.0 V
4.0
4.5 V
20 3.5 μA
4.0 60
kΩ
0.25
4
MHz
155 200 245 kHz
400
kHz
600
kHz
1.9 2.0 2.1 V
−50
+50 mV
0
100 μA
−3
+3 mV
−50
+50 nA
10
MHz
10
V/μs
0
2.7 V
−77 −80 −83 mV
0.05
2.7 V
500
μA
Rev. A | Page 3 of 24